MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 D Low Supply Voltage Range 1.8 V to 3.6 V D Ultralow-Power Consumption D Two Configurable Operational Amplifiers D D (MSP430x22x4 only) Brownout Detector Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Bootstrap Loader On Chip Emulation Module Family Members Include: MSP430F2232: 8KB + 256B Flash Memory 512B RAM MSP430F2252: 16KB + 256B Flash Memory 512B RAM MSP430F2272: 32KB + 256B Flash Memory 1KB RAM MSP430F2234: 8KB + 256B Flash Memory 512B RAM MSP430F2254: 16KB + 256B Flash Memory 512B RAM MSP430F2274: 32KB + 256B Flash Memory 1KB RAM Available in a 38-Pin Plastic Small-Outline Thin (TSSOP) Package and 40-Pin QFN Package For Complete Module Descriptions, Refer to the MSP430x2xx Family User's Guide D D D D D D D - Active Mode: 270 ?A at 1 MHz, 2.2 V - Standby Mode: 0.7 ?A - Off Mode (RAM Retention): 0.1 ?A Ultrafast Wake-Up From Standby Mode in Less Than 1 ?s 16-Bit RISC Architecture, 62.5 ns Instruction Cycle Time Basic Clock Module Configurations: - Internal Frequencies up to 16MHz With Four Calibrated Frequencies to ?1% - Internal Very Low Power LF Oscillator - 32-kHz Crystal - High-Frequency Crystal up to 16 MHz - Resonator - External Digital Clock Source - External resistor 16-Bit Timer_A With Three Capture/Compare Registers 16-Bit Timer_B With Three Capture/Compare Registers Universal Serial Communication Interface - Enhanced UART supporting Auto-Baudrate Detection (LIN) - IrDA Encoder and Decoder - Synchronous SPI - I2Ct 10-Bit, 200-ksps A/D Converter With Internal Reference, Sample-and-Hold, Autoscan, and Data Transfer Controller D D D D description The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 ?s. The MSP430x22xx series is an ultralow-power mixed signal microcontroller with two built-in 16-bit timers, a universal serial communication interface, 10-bit A/D converter with integrated reference and data transfer controller (DTC), two general purpose operational amplifiers in the MSP430x22x4 devices, and 32 I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand alone RF sensor front end is another area of application. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2006 Texas Instruments Incorporated POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 1 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 38-PIN TSSOP (DA) MSP430F2232IDA MSP430F2252IDA MSP430F2272IDA MSP430F2234IDA MSP430F2254IDA MSP430F2274IDA MSP430F2232TDA MSP430F2252TDA MSP430F2272TDA MSP430F2234TDA MSP430F2254TDA MSP430F2274TDA PLASTIC 40-PIN QFN (RHA) MSP430F2232IRHA MSP430F2252IRHA MSP430F2272IRHA MSP430F2234IRHA MSP430F2254IRHA MSP430F2274IRHA MSP430F2232TRHA MSP430F2252TRHA MSP430F2272TRHA MSP430F2234TRHA MSP430F2254TRHA MSP430F2274TRHA -40?C to 85?C -40?C to 105?C Product Preview 2 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 MSP430x22x2 device pinout, DA package TEST/SBWTCK DVCC P2.5/Rosc DVSS XOUT /P2.7 XIN /P2.6 RST /NMI /SBWTDIO P2.0/ACLK /A0 P2.1/TAINCLK /SMCLK /A1 P2.2/TA 0/A2 P3.0/UCB 0STE /UCA 0CLK /A5 P3.1/UCB 0SIMO /UCB 0SDA P3.2/UCB 0SOMI /UCB 0SCL P3.3/UCB 0CLK /UCA 0STE AVSS AVCC P4.0/TB 0 P4.1/TB 1 P4.2/TB 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 P1.7/TA 2/TDO /TDI P1.6/TA 1/TDI P1.5/TA 0/TMS P1.4/SMCLK /TCK P1.3/TA 2 P1.2/TA 1 P1.1/TA 0 P1.0/TACLK /ADC 10 CLK P2.4/TA 2/A4/VREF +/VeREF + P2.3/TA 1/A3/VREF - /VeREF - P3.7/A7 P3.6/A6 P3.5/UCA 0RXD /UCA 0SOMI P3.4/UCA 0TXD /UCA 0SIMO P4.7/TBCLK P4.6/TBOUTH /A15 P4.5/TB 2/A14 P4.4/TB 1/A13 P4.3/TB 0/A12 MSP430x22x4 device pinout, DA package TEST /SBWTCK DVCC P2.5/Rosc DVSS XOUT /P2.7 XIN /P2.6 RST /NMI /SBWTDIO P2.0/ACLK /A0/OA 0I0 P2.1/TAINCLK /SMCLK /A1/OA 0O P2.2/TA 0/A2/OA 0I1 P3.0/UCB 0STE /UCA 0CLK /A5 P3.1/UCB 0SIMO /UCB 0SDA P3.2/UCB 0SOMI /UCB 0SCL P3.3/UCB 0CLK /UCA 0STE AVSS AVCC P4.0/TB 0 P4.1/TB 1 P4.2/TB 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 P1.7/TA 2/TDO /TDI P1.6/TA 1/TDI P1.5/TA 0/TMS P1.4/SMCLK /TCK P1.3/TA 2 P1.2/TA 1 P1.1/TA 0 P1.0/TACLK /ADC 10 CLK P2.4/TA 2/A4/VREF +/VeREF +/OA 1I0 P2.3/TA 1/A3/VREF - /VeREF - /OA 1I1/OA 1O P3.7/A7/OA 1I2 P3.6/A6/OA 0I2 P3.5/UCA 0RXD /UCA 0SOMI P3.4/UCA 0TXD /UCA 0SIMO P4.7/TBCLK P4.6/TBOUTH /A15 /OA 1I3 P4.5/TB 2/A14 /OA 0I3 P4.4/TB 1/A13 /OA 1O P4.3/TB 0/A12 /OA 0O POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 3 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 MSP430x22x2 device pinout, RHA package P1.6/TA1/TDI/TCLK P1.7/TA2/TDO/TDI P1.4/SMCLK/TCK TEST/SBWTCK P1.5/TA0/TMS P2.5/Rosc P1.3/TA2 DVSS XOUT /P2.7 XIN /P2.6 DVSS RST /NMI /SBWTDIO P2.0/ACLK /A0 P2.1/TAINCLK /SMCLK /A1 P2.2/TA 0/A2 P3.0/UCB 0STE /UCA 0CLK /A5 P3.1/UCB 0SIMO /UCB 0SDA 1 2 3 4 5 6 7 8 9 10 39 38 37 36 35 34 33 32 P1.2/TA1 30 29 28 27 26 25 24 23 22 21 P1.1/TA 0 P1.0/TACLK /ADC 10 CLK P2.4/TA 2/A4/VREF +/VeREF + P2.3/TA 1/A3/VREF - /VeREF - P3.7/A7 P3.6/A6 P3.5/UCA 0RXD /UCA 0SOMI P3.4/UCA 0TXD /UCA 0SIMO P4.7/TBCLK P4.6/TBOUTH /A15 P4.5/TB2/A14 DVCC P3.3/UCB0CLK/UCA0STE 12 13 14 15 16 17 18 19 P4.3/TB0/A12 P3.2/UCB0SOMI/UCB0SCL P4.4/TB1/A13 P4.0/TB0 P4.1/TB1 P4.2/TB2 AVSS AVCC DVCC 4 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 MSP430x22x4 device pinout, RHA package P1.6/TA1/TDI/TCLK P1.7/TA2/TDO/TDI P1.4/SMCLK/TCK TEST/SBWTCK P1.5/TA0/TMS P2.5/Rosc P1.3/TA2 DVSS XOUT /P2.7 XIN /P2.6 DVSS RST /NMI /SBWTDIO P2.0/ACLK /A0/OA 0I0 P2.1/TAINCLK /SMCLK /A1/OA 0O P2.2/TA 0/A2/OA 0I1 P3.0/UCB 0STE /UCA 0CLK /A5 P3.1/UCB 0SIMO /UCB 0SDA 1 2 3 4 5 6 7 8 9 10 39 38 37 36 35 34 33 32 P1.2/TA1 30 29 28 27 26 25 24 23 22 21 P1.1/TA 0 P1.0/TACLK /ADC 10 CLK P2.4/TA 2/A4/VREF +/VeREF +/OA 1I0 P2.3/TA 1/A3/VREF - /VeREF - /OA 1I1/OA 1O P3.7/A7/OA 1I2 P3.6/A6/OA 0I2 P3.5/UCA 0RXD /UCA 0SOMI P3.4/UCA 0TXD /UCA 0SIMO P4.7/TBCLK P4.6/TBOUTH /A15 /OA 1I3 P4.5/TB2/A14/OA0I3 DVCC P3.3/UCB0CLK/UCA0STE 12 13 14 15 16 17 18 19 P4.0/TB0 P4.1/TB1 P4.2/TB2 AVSS AVCC P4.3/TB0/A12/OA0O P3.2/UCB0SOMI/UCB0SCL P4.4/TB1/A13/OA1O DVCC POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 5 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 MSP430x22x2 functional block diagram VCC VSS P1.x/P2.x 2x8 XIN XOUT ACLK SMCLK Flash 32kB 16kB 8kB RAM 1kB 512B 512B ADC10 10- Bit 12 Channels, Autoscan, DTC Ports P1/P2 Ports P3/P4 2x8 I/O Interrupt capability, pull- up/down resistors 2x8 I/O pull- up/down resistors P3.x/P4.x 2x8 Basic Clock System+ MCLK 16MHz CPU incl. 16 Registers MAB MDB Emulation (2BP) JTAG Interface Spy- Wire Bi Brownout Protection Watchdog WDT+ 15/16- Bit Timer_A3 3 CC Registers Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C RST/NMI NOTE: See port schematics section for detailed I/O information. MSP430x22x4 functional block diagram VCC VSS P1.x/P2.x 2x8 XIN XOUT ACLK SMCLK Flash 32kB 16kB 8kB RAM 1kB 512B 512B ADC10 10- Bit OA0, OA1 12 Channels, Autoscan, DTC 2 Op Amps Ports P1/P2 Ports P3/P4 2x8 I/O Interrupt capability, pull- up/down resistors 2x8 I/O pull- up/down resistors P3.x/P4.x 2x8 Basic Clock System+ MCLK 16MHz CPU incl. 16 Registers MAB MDB Emulation (2BP) JTAG Interface Spy- Wire Bi Brownout Protection Watchdog WDT+ 15/16- Bit Timer_A3 3 CC Registers Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C RST/NMI NOTE: See port schematics section for detailed I/O information. 6 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Terminal Functions, MSP430x22x2 TERMINAL NAME P1.0/TACLK/ ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK/ TCK P1.5/TA0/ TMS P1.6/TA1/ TDI/TCLK P1.7/TA2/ TDO/TDI P2.0/ACLK/A0 P2.1/TAINCLK/SMCLK/A1 DA NO. 31 RHA NO. 29 I/O I/O DESCRIPTION General-purpose digital I/O pin Timer_A, clock signal TACLK input ADC10, conversion clock General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: OUT1 output General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: OUT2 output General-purpose digital I/O pin / SMCLK signal output Test Clock input for device programming and test General-purpose digital I/O pin / Timer_A, compare: OUT0 output Test Mode Select input for device programming and test General-purpose digital I/O pin / Timer_A, compare: OUT1 output Test Data Input or Test Clock Input for programming and test General-purpose digital I/O pin / Timer_A, compare: OUT2 output Test Data Output or Test Data Input for programming and test General-purpose digital I/O pin / ACLK output ADC10, analog input A0 General-purpose digital I/O pin Timer_A, clock signal at INCLK, SMCLK signal output ADC10, analog input A1 General-purpose digital I/O pin Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2 General-purpose digital I/O pin Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 / negative reference voltage output/input General-purpose digital I/O pin / Timer_A, compare: OUT2 output ADC10, analog input A4 / positive reference voltage output/input General-purpose digital I/O pin Input for external DCO resistor to define DCO frequency Input terminal of crystal oscillator General-purpose digital I/O pin Output terminal of crystal oscillator General-purpose digital I/O pin General-purpose digital I/O pin USCI_B0 slave transmit enable / USCI_A0 clock input/output ADC10, analog input A5 General-purpose digital I/O pin USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode General-purpose digital I/O pin USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode General-purpose digital I/O pin USCI_B0 clock input/output / USCI_A0 slave transmit enable General-purpose digital I/O pin USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode 32 33 34 35 36 37 38 8 9 30 31 32 33 34 35 36 6 7 I/O I/O I/O I/O I/O I/O I/O I/O I/O P2.2/TA0/A2 10 8 I/O P2.3/TA1/ A3/VREF-/VeREF- P2.4/TA2/ A4/VREF+/VeREF+ P2.5/ ROSC XIN/P2.6 XOUT/P2.7 P3.0/ UCB0STE/UCA0CLK/ A5 P3.1/ UCB0SIMO/UCB0SDA P3.2/ UCB0SOMI/UCB0SCL P3.3/ UCB0CLK/UCA0STE P3.4/ UCA0TXD/UCA0SIMO 29 27 I/O 30 3 6 5 11 28 40 3 2 9 I/O I/O I/O I/O I/O 12 13 14 25 10 11 12 23 I/O I/O I/O I/O POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 7 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Terminal Functions, MSP430x22x2 (Continued) TERMINAL NAME P3.5/ UCA0RXD/UCA0SOMI P3.6/A6 P3.7/A7 P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB0/ A12 P4.4/TB1 A13 P4.5/TB2 A14 P4.6/TBOUTH A15 P4.7/TBCLK RST/NMI/SBWTDIO TEST/SBWTCK DA NO. 26 27 28 17 18 19 20 RHA NO. 24 25 26 15 16 17 18 I/O I/O I/O I/O I/O I/O I/O I/O DESCRIPTION General-purpose digital I/O pin USCI_A0 receive data input in UART mode, slave out/master in in SPI mode General-purpose digital I/O pin ADC10 analog input A6 General-purpose digital I/O pin ADC10 analog input A7 General-purpose digital I/O pin Timer_B, capture: CCI0A input, compare: OUT0 output General-purpose digital I/O pin Timer_B, capture: CCI1A input, compare: OUT1 output General-purpose digital I/O pin Timer_B, capture: CCI2A input, compare: OUT2 output General-purpose digital I/O pin Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12 General-purpose digital I/O pin Timer_B, capture: CCI1B input, compare: OUT1 output ADC10 analog input A13 General-purpose digital I/O pin Timer_B, compare: OUT2 output ADC10 analog input A14 General-purpose digital I/O pin Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15 General-purpose digital I/O pin Timer_B, clock signal TBCLK input Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test Digital supply voltage Analog supply voltage Digital ground reference Analog ground reference NA QFN package pad; connection to DVSS recommended. 21 19 I/O 22 20 I/O 23 21 I/O 24 7 1 22 5 37 I/O I I DVCC AVCC DVSS AVSS QFN Pad 2 16 4 15 NA 38, 39 14 1, 4 13 Package Pad TDO or TDI is selected via JTAG instruction. NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. 8 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Terminal Functions, MSP430x22x4 TERMINAL NAME P1.0/TACLK/ ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK/ TCK P1.5/TA0/ TMS P1.6/TA1/ TDI/TCLK P1.7/TA2/ TDO/TDI P2.0/ACLK/A0/OA0I0 P2.1/TAINCLK/SMCLK/ A1/OA0O P2.2/TA0/ A2/OA0I1 P2.3/TA1/ A3/VREF-/VeREF- /OA1I1/OA1O P2.4/TA2/ A4/VREF+/VeREF+ /OA1I0 P2.5/ ROSC XIN/P2.6 XOUT/P2.7 P3.0/ UCB0STE/UCA0CLK/ A5 P3.1/ UCB0SIMO/UCB0SDA P3.2/ UCB01SOMI/UCB0SCL P3.3/ UCB0CLK/UCA0STE P3.4/ UCA0TXD/UCA0SIMO DA NO. 31 RHA NO. 29 I/O I/O DESCRIPTION General-purpose digital I/O pin Timer_A, clock signal TACLK input ADC10, conversion clock General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: OUT1 output General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: OUT2 output General-purpose digital I/O pin / SMCLK signal output Test Clock input for device programming and test General-purpose digital I/O pin / Timer_A, compare: OUT0 output Test Mode Select input for device programming and test General-purpose digital I/O pin / Timer_A, compare: OUT1 output Test Data Input or Test Clock Input for programming and test General-purpose digital I/O pin / Timer_A, compare: OUT2 output Test Data Output or Test Data Input for programming and test General-purpose digital I/O pin / ACLK output ADC10, analog input A0 / OA0, analog input I0 General-purpose digital I/O pin / Timer_A, clock signal at INCLK SMCLK signal output ADC10, analog input A1 / OA0, analog output General-purpose digital I/O pin Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2 / OA0, analog input I1 General-purpose digital I/O pin Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 / negative reference voltage output/input OA1, analog input I1 / OA1, analog output General-purpose digital I/O pin / Timer_A, compare: OUT2 output ADC10, analog input A4 / positive reference voltage output/input OA1, analog input I0 General-purpose digital I/O pin Input for external DCO resistor to define DCO frequency Input terminal of crystal oscillator General-purpose digital I/O pin Output terminal of crystal oscillator General-purpose digital I/O pin General-purpose digital I/O pin USCI_B0 slave transmit enable / USCI_A0 clock input/output ADC10, analog input A5 General-purpose digital I/O pin USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode General-purpose digital I/O pin USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode General-purpose digital I/O pin USCI_B0 clock input/output / USCI_A0 slave transmit enable General-purpose digital I/O pin USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode 32 33 34 35 36 37 38 8 9 30 31 32 33 34 35 36 6 7 I/O I/O I/O I/O I/O I/O I/O I/O I/O 10 8 I/O 29 27 I/O 30 28 I/O 3 6 5 11 40 3 2 9 I/O I/O I/O I/O 12 13 14 25 10 11 12 23 I/O I/O I/O I/O POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 9 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Terminal Functions, MSP430x22x4 (Continued) TERMINAL NAME P3.5/ UCA0RXD/UCA0SOMI P3.6/A6/OA0I2 P3.7/A7/OA1I2 P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB0/ A12/OA0O P4.4/TB1 A13/OA1O P4.5/TB2 A14/OA0I3 P4.6/TBOUTH A15/OA1I3 P4.7/TBCLK RST/NMI/SBWTDIO TEST/SBWTCK DA NO. 26 27 28 17 18 19 20 RHA NO. 24 25 26 15 16 17 18 I/O I/O I/O I/O I/O I/O I/O I/O DESCRIPTION General-purpose digital I/O pin USCI_A0 receive data input in UART mode, slave out/master in in SPI mode General-purpose digital I/O pin ADC10 analog input A6 / OA0 analog input I2 General-purpose digital I/O pin ADC10 analog input A7 / OA1 analog input I2 General-purpose digital I/O pin Timer_B, capture: CCI0A input, compare: OUT0 output General-purpose digital I/O pin Timer_B, capture: CCI1A input, compare: OUT1 output General-purpose digital I/O pin Timer_B, capture: CCI2A input, compare: OUT2 output General-purpose digital I/O pin Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12 / OA0 analog output General-purpose digital I/O pin Timer_B, capture: CCI1B input, compare: OUT1 output ADC10 analog input A13 / OA1 analog output General-purpose digital I/O pin Timer_B, compare: OUT2 output ADC10 analog input A14 / OA0 analog input I3 General-purpose digital I/O pin Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15 / OA1 analog input I3 General-purpose digital I/O pin Timer_B, clock signal TBCLK input Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test Digital supply voltage Analog supply voltage Digital ground reference Analog ground reference NA QFN package pad connection to DVSS recommended. 21 19 I/O 22 20 I/O 23 21 I/O 24 7 1 22 5 37 I/O I I DVCC AVCC DVSS AVSS QFN Pad 2 16 4 15 NA 38, 39 14 1, 4 13 Package Pad TDO or TDI is selected via JTAG instruction. NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. 10 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2. Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Table 1. Instruction Word Formats Dual operands, source-destination Single operands, destination only Relative jump, un/conditional e.g., ADD R4,R5 e.g., CALL e.g., JNE R8 R4 + R5 ---> R5 PC --> (TOS), R8--> PC Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate NOTE: S = source S D F F F F F F F F F F F D = destination SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV &MEM,&TCDAT MOV @Rn,Y(Rm) MOV @Rn+,Rm MOV #X,TONI MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) OPERATION R10 --> R11 M(2+R5)--> M(6+R6) M(EDE) --> M(TONI) M(MEM) --> M(TCDAT) M(R10) --> M(Tab+R6) M(R10) --> R11 R10 + 2--> R10 #45 --> M(TONI) POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 11 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode AM; - All clocks are active D Low-power mode 0 (LPM0); - CPU is disabled ACLK and SMCLK remain active. MCLK is disabled D Low-power mode 1 (LPM1); - CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO's dc-generator is disabled if DCO not used in active mode D Low-power mode 2 (LPM2); - CPU is disabled MCLK and SMCLK are disabled DCO's dc-generator remains enabled ACLK remains active D Low-power mode 3 (LPM3); - CPU is disabled MCLK and SMCLK are disabled DCO's dc-generator is disabled ACLK remains active D Low-power mode 4 (LPM4); - CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO's dc-generator is disabled Crystal oscillator is stopped 12 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh-0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will go into LPM4 immediately after power-up. INTERRUPT SOURCE Power-up External reset Watchdog Flash key violation PC out-of-range (see Note 1) NMI Oscillator fault Flash memory access violation Timer_B3 Timer_B3 INTERRUPT FLAG PORIFG RSTIFG WDTIFG KEYV (see Note 2) NMIIFG OFIFG ACCVIFG (see Notes 2 & 4) TBCCR0 CCIFG (see Note 3) TBCCR1 and TBCCR2 CCIFGs, TBIFG (see Notes 2 & 3) WDTIFG TACCR0 CCIFG (see Note 3) TACCR1 CCIFG. TACCR2 CCIFG TAIFG (see Notes 2 & 3) UCA0RXIFG, UCB0RXIFG (see Notes 2) UCA0TXIFG, UCB0TXIFG (see Notes 2) ADC10IFG (see Note 3) P2IFG.0 to P2IFG.7 (see Notes 2 & 3) P1IFG.0 to P1IFG.7 (see Notes 2 & 3) SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset 0FFFEh 31, highest (non)-maskable, (non)-maskable, (non)-maskable maskable maskable 0FFFCh 30 0FFFAh 0FFF8h 0FFF6h 29 28 27 26 25 24 Watchdog Timer Timer_A3 Timer_A3 maskable maskable maskable 0FFF4h 0FFF2h 0FFF0h USCI_A0/USCI_B0 Receive USCI_A0/USCI_B0 Transmit ADC10 I/O Port P2 (eight flags) I/O Port P1 (eight flags) maskable maskable maskable 0FFEEh 0FFECh 0FFEAh 0FFE8h 23 22 21 20 19 18 17 16 15 14 ... 0, lowest maskable maskable 0FFE6h 0FFE4h 0FFE2h 0FFE0h (see Note 5) (see Note 6) 0FFDEh 0FFDCh ... 0FFC0h NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h-01FFh) or from within unused address ranges. 2. Multiple source flags 3. Interrupt flags are located in the module 4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. 5. This location is used as bootstrap loader security key (BSLSKEY). A 0AA55h at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied. 6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if necessary. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 13 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 Address 00h 7 6 5 ACCVIE rw-0 WDTIE OFIE NMIIE ACCVIE Address 01h 7 4 NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0 Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Oscillator fault enable (Non)maskable interrupt enable Flash access violation interrupt enable 6 5 4 3 UCB0TXIE rw-0 2 UCB0RXIE rw-0 1 UCA0TXIE rw-0 0 UCA0RXIE rw-0 UCA0RXIE UCA0TXIE UCB0RXIE UCB0TXIE USCI_A0 receive-interrupt enable USCI_A0 transmit-interrupt enable USCI_B0 receive-interrupt enable USCI_B0 transmit-interrupt enable 14 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 interrupt flag register 1 and 2 Address 02h 7 6 5 4 NMIIFG rw-0 WDTIFG OFIFG RSTIFG PORIFG NMIIFG Address 03h 7 3 RSTIFG rw-(0) 2 PORIFG rw-(1) 1 OFIFG rw-1 0 WDTIFG rw-(0) Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. Flag set on oscillator fault External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up Power-On interrupt flag. Set on VCC power-up. Set via RST/NMI-pin 6 5 4 3 UCB0 TXIFG rw-1 2 UCB0 RXIFG rw-0 1 UCA0 TXIFG rw-1 0 UCA0 RXIFG rw-0 UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG Legend rw: rw-0,1: rw-(0,1): USCI_A0 receive-interrupt flag USCI_A0 transmit-interrupt flag USCI_B0 receive-interrupt flag USCI_B0 transmit-interrupt flag Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 15 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 memory organization MSP430F223x Memory Main: interrupt vector Main: code memory Information memory Boot memory RAM Peripherals Size Flash Flash Size Flash Size ROM Size 16-bit 8-bit 8-bit SFR 8KB Flash 0FFFFh-0FFC0h 0FFFFh-0E000h 256 Byte 010FFh-01000h 1KB 0FFFh-0C00h 512 Byte 03FFh-0200h 01FFh-0100h 0FFh-010h 0Fh-00h MSP430F225x 16KB Flash 0FFFFh-0FFC0h 0FFFFh-0C000h 256 Byte 010FFh-01000h 1KB 0FFFh-0C00h 512 Byte 03FFh-0200h 01FFh-0100h 0FFh-010h 0Fh-00h MSP430F227x 32KB Flash 0FFFFh-0FFC0h 0FFFFh-08000h 256 Byte 010FFh-01000h 1KB 0FFFh-0C00h 1KB 05FFh-0200h 01FFh-0100h 0FFh-010h 0Fh-00h bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report, Features of the MSP430 Bootstrap Loader, TI literature number SLAA089. BSL Function Data Transmit Data Receive DA Package Pins 32 - P1.1 10 - P2.2 RHA Package Pins 30 - P1.1 8 - P2.2 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A to D can be erased individually, or as a group with segments 0-n. Segments A to D are also called information memory. D Segment A contains calibration data. After reset, segment A is protected against programming or erasing. It can be unlocked, but care should be taken not to erase this segment if the calibration data is required. 16 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x2xx Family User's Guide. oscillator and system clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very low power, low frequency oscillator, an internal digitally-controlled oscillator (DCO), and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 ?s. The basic clock module provides the following clock signals: D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or the internal very D D low power LF oscillator. Main clock (MCLK), the system clock used by the CPU. Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. DCO Calibration Data (provided from factory in flash info memory segment A, see Note) DCO Frequency 1 MHz 8 MHz 12 MHz 16 MHz Calibration Register CALBC1_1MHZ CALDCO_1MHZ CALBC1_8MHZ CALDCO_8MHZ CALBC1_12MHZ CALDCO_12MHZ CALBC1_16MHZ CALDCO_16MHZ Size byte byte byte byte byte byte byte byte Address 010FFh 010FEh 010FDh 010FCh 010FBh 010FAh 010F9h 010F8h brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. digital I/O There are four 8-bit I/O ports implemented--ports P1, P2, P3, and P4: D D D D D All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of port P1 and P2. Read/write access to port-control registers is supported by all instructions. Each I/O has an individually programmable pullup/pulldown resistor. WDT+ watchdog timer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 17 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number DA 31 - P1.0 RHA 29 - P1.0 TACLK ACLK SMCLK 9 - P2.1 32 - P1.1 10 - P2.2 7 - P2.1 30 - P1.1 8 - P2.2 TAINCLK TA0 TA0 VSS VCC TA1 TA1 VSS VCC 34 - P1.3 32 - P1.3 TA2 ACLK (internal) VSS VCC TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 CCR1 TA1 CCR0 TA0 32 - P1.1 10 - P2.2 36 - P1.5 33 - P1.2 29 - P2.3 37 - P1.6 34 - P1.3 30 - P2.4 38 - P1.7 30 - P1.1 8 - P2.2 34 - P1.5 31 - P1.2 27 - P2.3 35 - P1.6 32 - P1.3 28 - P2.4 36 - P1.7 Timer NA Device Input Signal Module Input Name Module Block Module Output Signal DA Output Pin Number RHA 33 - P1.2 29 - P2.3 31 - P1.2 27 - P2.3 18 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 timer_B3 Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_B3 Signal Connections Input Pin Number DA 24 - P4.7 RHA 22 - P4.7 TBCLK ACLK SMCLK 24 - P4.7 17 - P4.0 20 - P4.3 22 - P4.7 15 - P4.0 18 - P4.3 TBCLK TB0 TB0 VSS VCC TB1 TB1 VSS VCC 19 - P4.2 17 - P4.2 TB2 ACLK (internal) VSS VCC TBCLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TB2 CCR1 TB1 CCR0 TB0 17 - P4.0 20 - P4.3 15 - P4.0 18 - P4.3 Timer NA Device Input Signal Module Input Name Module Block Module Output Signal DA Output Pin Number RHA 18 - P4.1 21 - P4.4 16 - P4.1 19 - P4.4 18 - P4.1 21 - P4.4 16 - P4.1 19 - P4.4 19 - P4.2 22 - P4.5 17 - P4.2 20 - P4.5 USCI The universal serial communication interface (USCI) module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA. USCI_B0 provides support for SPI (3 or 4 pin) and I2C. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 19 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 ADC10 The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion result handling allowing ADC samples to be converted and stored without any CPU intervention. operational amplifier OA (MSP430x22x4 only) The MSP430x22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion. OA0 Signal Connections Analog Input Pin Number DA 8 - A0 10 - A2 10 - A2 27 - A6 22 - A14 RHA 6 - A0 8 - A2 8 - A2 25 - A6 20 - A14 OA0I0 OA0I1 OA0I1 OA0I2 OA0I3 OAxI0 OA0I1 OAxI1 OAxIA OAxIB Device Input Signal Module Input Name OA1 Signal Connections Analog Input Pin Number DA 30 - A4 10 - A2 29 - A3 28 - A7 23 - A15 RHA 28 - A4 8 - A2 27 - A3 26 - A7 21 - A15 OA1I0 OA0I1 OA1I1 OA1I2 OA1I3 OAxI0 OA0I1 OAxI1 OAxIA OAxIB Device Input Signal Module Input Name 20 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 peripheral file map PERIPHERALS WITH WORD ACCESS ADC10 ADC data transfer start address ADC memory ADC control register 1 ADC control register 0 ADC analog enable 0 ADC analog enable 1 ADC data transfer control register 1 ADC data transfer control register 0 Capture/compare register Capture/compare register Capture/compare register Timer_B register Capture/compare control Capture/compare control Capture/compare control Timer_B control Timer_B interrupt vector Capture/compare register Capture/compare register Capture/compare register Timer_A register Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector Flash control 3 Flash control 2 Flash control 1 Watchdog/timer control PERIPHERALS WITH BYTE ACCESS OA1 (MSP430x22x4 only) OA0 (MSP430x22x4 only) USCI_B0 Operational Amplifier 1 control register 1 Operational Amplifier 1 control register 1 Operational Amplifier 0 control register 1 Operational Amplifier 0 control register 1 USCI_B0 transmit buffer USCI_B0 receive buffer USCI_B0 status USCI_B0 bit rate control 1 USCI_B0 bit rate control 0 USCI_B0 control 1 USCI_B0 control 0 USCI_B0 I2C slave address USCI_B0 I2C own address USCI_A0 transmit buffer USCI_A0 receive buffer USCI_A0 status USCI_A0 modulation control USCI_A0 baud rate control 1 USCI_A0 baud rate control 0 USCI_A0 control 1 USCI_A0 control 0 USCI_A0 IrDA receive control USCI_A0 IrDA transmit control USCI_A0 auto baud rate control OA1CTL1 OA1CTL0 OA0CTL1 OA0CTL0 UCB0TXBUF UCB0RXBUF UCB0STAT UCB0BR1 UCB0BR0 UCB0CTL1 UCB0CTL0 UCB0SA UCB0OA UCA0TXBUF UCA0RXBUF UCA0STAT UCA0MCTL UCA0BR1 UCA0BR0 UCA0CTL1 UCA0CTL0 UCA0IRRCTL UCA0IRTCTL UCA0ABCTL 0C3h 0C2h 0C1h 0C0h 06Fh 06Eh 06Dh 06Bh 06Ah 069h 068h 011Ah 0118h 067h 066h 065h 064h 063h 062h 061h 060h 05Fh 05Eh 05Dh ADC10SA ADC10MEM ADC10CTL1 ADC10CTL0 ADC10AE0 ADC10AE1 ADC10DTC1 ADC10DTC0 TBCCR2 TBCCR1 TBCCR0 TBR TBCCTL2 TBCCTL1 TBCCTL0 TBCTL TBIV TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TACTL TAIV FCTL3 FCTL2 FCTL1 WDTCTL 1BCh 1B4h 1B2h 1B0h 04Ah 04Bh 049h 048h 0196h 0194h 0192h 0190h 0186h 0184h 0182h 0180h 011Eh 0176h 0174h 0172h 0170h 0166h 0164h 0162h 0160h 012Eh 012Ch 012Ah 0128h 0120h Timer_B Timer_A Flash Memory Watchdog Timer+ USCI_A0 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 21 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 PERIPHERALS WITH BYTE ACCESS (continued) Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control Port P4 resistor enable Port P4 selection Port P4 direction Port P4 output Port P4 input Port P3 resistor enable Port P3 selection Port P3 direction Port P3 output Port P3 input Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL P4REN P4SEL P4DIR P4OUT P4IN P3REN P3SEL P3DIR P3OUT P3IN P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN IFG2 IFG1 IE2 IE1 053h 058h 057h 056h 011h 01Fh 01Eh 01Dh 01Ch 010h 01Bh 01Ah 019h 018h 02Fh 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 027h 026h 025h 024h 023h 022h 021h 020h 003h 002h 001h 000h Port P4 Port P3 Port P2 Port P1 Special Function 22 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 absolute maximum ratings (see Note 1) Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.1 V Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?2 mA Storage temperature, Tstg (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . -55?C to 150?C Storage temperature, Tstg (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . -40?C to 105?C NOTES: 1. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. 3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. recommended operating conditions MIN Supply voltage during program execution, VCC Supply voltage during program/erase flash memory, VCC Supply voltage, VSS I Version Operating free-air temperature range, TA T Version VCC = 1.8 V, Duty Cycle = 50% ?10% Processor frequency fSYSTEM (Maximum MCLK frequency) (see Notes 1, 2 and Figure 1) VCC = 2.7 V, Duty Cycle = 50% ?10% VCC 3.3 V, Duty Cycle = 50% ?10% -40 -40 dc dc dc 1.8 2.2 0 85 105 4.15 12 16 MHz NOM MAX 3.6 3.6 UNIT V V V ?C ?C NOTES: 1. The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet. Legend: 12 MHz 7.5 MHz 4.15 MHz 1.8 V 2.2 V 2.7 V 3.3 V 3.6 V Supply Voltage -V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Operating Area POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 ??? ??? ??? ??? ??? ??? ????????? ????????? ????????? ????????? ????????? ????????? ????????? ????????? ????????? ????????? 16 MHz System Frequency -MHz Supply voltage range, during flash memory programming Supply voltage range, during program execution 23 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) active mode supply current (into DVCC + AVCC) excluding external current (see Notes 1 and 2) PARAMETER TEST CONDITIONS fDCO = fMCLK = fSMCLK = 1MHz, fACLK = 32,768Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 1MHz, fACLK = 32,768Hz, Program executes in RAM, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 fMCLK = fSMCLK = fACLK = 32,768Hz/8 = 4,096Hz, fDCO = 0Hz, Program executes in flash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0 fMCLK = fSMCLK = fDCO(0, 0) 100kHz, DCO(0,0) fACLK = 0Hz, Program executes in flash, RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1 -40-85?C 105?C -40-85?C 105?C -40-85?C 105?C -40-85?C 105?C TA VCC 2.2 V MIN TYP 270 MAX 390 ?A 3V 390 550 UNIT IAM, 1MHz Active mode (AM) current (1MHz) 2.2 V 240 ?A IAM, 1MHz Active mode (AM) current (1MHz) 3V 340 2.2 V 2.2 V 3V 3V 2.2 V 2.2 V 3V 3V 5 9 18 ?A IAM, 4kHz Active mode (AM) current (4kHz) 6 10 20 60 85 95 ?A IAM,100kHz Active mode (AM) current (100kHz) 72 95 105 NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. 2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9pF. 24 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics - active mode supply current (into DVCC + AVCC) 8.0 7.0 Active Mode Current - mA 6.0 fDCO = 12 MHz 5.0 4.0 3.0 2.0 1.0 0.0 1.5 fDCO = 16 MHz Active Mode Current - mA 4.0 5.0 TA = 85 ?C TA = 25 ?C 3.0 VCC = 3 V 2.0 fDCO = 8 MHz TA = 85 ?C TA = 25 ?C 1.0 fDCO = 1 MHz 2.0 2.5 3.0 3.5 4.0 0.0 0.0 VCC = 2.2 V 4.0 8.0 12.0 16.0 VCC - Supply Voltage - V fDCO - DCO Frequency - MHz Figure 2. Active mode current vs VCC, TA = 25?C Figure 3. Active mode current vs DCO frequency POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 25 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) low power mode supply currents (into DVCC + AVCC) excluding external current (see Notes 1 and 2) PARAMETER TEST CONDITIONS fMCLK = 0MHz, fSMCLK = fDCO = 1MHz, fACLK = 32,768Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 fMCLK = 0MHz, fSMCLK = fDCO(0, 0) 100kHz, fACLK = 0Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1 fMCLK = fSMCLK = 0MHz, fDCO = 1MHz, fACLK = 32,768Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 -40-85?C 2.2 V 105?C -40-85?C 3V 105?C -40?C 25?C Low-power mode 3 (LPM3) current, ILPM3,LFXT1 see Note 4 fDCO = fMCLK = fSMCLK = 0MHz, fACLK = 32,768Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 85?C 105?C -40?C 25?C 85?C 105?C -40?C 25?C Low-power mode 3 current, (LPM3) see Note 4 fDCO = fMCLK = fSMCLK = 0MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 85?C 105?C -40?C 25?C 85?C 105?C Low-power mode 4 (LPM4) current, see Note 5 fDCO = fMCLK = fSMCLK = 0MHz, fACLK = 0Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 -40?C 25?C 85?C 105?C 2.2 V/3 V 3V 2.2 V 3V 2.2 V 0.7 0.7 2.8 6 0.9 0.9 3.0 6.5 0.4 0.5 2.2 5.7 0.5 0.6 2.5 6.0 0.1 0.1 1.9 5.5 40 1.4 1.4 4.5 18 1.5 1.5 5.0 19 1.0 1.0 4.2 16.5 1.2 1.2 4.5 17 0.5 0.5 4.0 16 A ?A ?A ?A ?A ?A 25 35 32 ?A TA VCC 2.2 V MIN TYP 75 MAX 90 ?A 3V 90 120 UNIT ILPM0, 1MHz Low-power mode 0 (LPM0) current, see Note 3 Low-power mode ILPM0, 100kHz 0 (LPM0) current, see Note 3 2.2 V 37 48 ?A 3V 41 22 65 29 ILPM2 Low-power mode 2 (LPM2) current, see Note 4 ILPM3,VLO ILPM4 NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. 2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9pF. 3. Current for brownout and WDT clocked by SMCLK included. 4. Current for brownout and WDT clocked by ACLK included. 5. Current for brownout included. 26 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs - Ports P1, P2, P3, P4, and RST/NMI PARAMETER Positive-going input threshold voltage TEST CONDITIONS VCC 2.2 V 3V Negative-going input threshold voltage Input voltage hysteresis (VIT+ - VIT-) Pullup/pulldown resistor Input Capacitance For pullup: VIN = VSS; For pulldown: VIN = VCC VIN = VSS or VCC 2.2 V 3V Vhys RPull CI 2.2 V 3V MIN 0.45 VIT+ 1.00 1.35 0.25 VIT- 0.55 0.75 0.2 0.3 20 35 5 TYP MAX 0.75 1.65 2.25 0.55 1.20 1.65 1.0 1.0 50 V V kW pF V VCC UNIT VCC inputs - Ports P1 and P2 PARAMETER t(int) External interrupt timing TEST CONDITIONS Port P1, P2: P1.x to P2.x, External trigger puls width to set interrupt flag, (see Note 1) VCC 2.2 V/3 V MIN 20 TYP MAX UNIT ns NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals shorter than t(int). leakage current - Ports P1, P2, P3 and P4 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Ilkg(Px.x) High-impedance leakage current see Notes 1 and 2 2.2 V/3 V ?50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 27 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs - Ports P1, P2, P3 and P4 PARAMETER TEST CONDITIONS I(OHmax) = -1.5 mA (see Notes 1) I(OHmax) = -6 mA (see Notes 2) I(OHmax) = -1.5 mA (see Notes 1) I(OHmax) = -6 mA (see Notes 2) I(OLmax) = 1.5 mA (see Notes 1) I(OLmax) = 6 mA (see Notes 2) I(OLmax) = 1.5 mA (see Notes 1) VCC 2.2 V 2.2 V 3V 3V 2.2 V 2.2 V 3V MIN VCC-0.25 VCC-0.6 VCC-0.25 VCC-0.6 VSS VSS VSS TYP MAX VCC VCC VCC VCC VSS+0.25 VSS+0.6 VSS+0.25 UNIT VOH High-level output voltage V VOL Low-level output voltage V I(OLmax) = 6 mA (see Notes 2) 3V VSS VSS+0.6 NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ?12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ?48 mA to hold the maximum voltage drop specified. output frequency - Ports P1, P2, P3 and P4 PARAMETER fPx.y Port output frequency (with load) Clock output frequency TEST CONDITIONS P1.4/SMCLK, CL = 20 pF, RL = 1 kW against VCC/2 (see Note 1 and 2) P2.0/ACLK, P1.4/SMCLK, CL = 20 pF (see Note 2) VCC 2.2 V 3V 2.2 V 3V MIN TYP MAX 10 12 12 16 UNIT MHz MHz MHz MHz fPort_CLK NOTES: 1. Alternatively a resistive divider with 2 times 2 kW between VCC and VSS is used as load. The output is connected to the center tap of the divider. 2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. 28 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics - outputs TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 25.0 I OL - Typical Low-Level Output Current - mA VCC = 2.2 V P4.5 20.0 TA = 25?C TA = 85?C I OL - Typical Low-Level Output Current - mA 50.0 VCC = 3 V P4.5 40.0 TA = 85?C 30.0 TA = 25?C TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 15.0 10.0 20.0 5.0 10.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL - Low-Level Output Voltage - V VOL - Low-Level Output Voltage - V Figure 4 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 I OH - Typical High-Level Output Current - mA I OH - Typical High-Level Output Current - mA VCC = 2.2 V P4.5 -5.0 0.0 VCC = 3 V P4.5 -10.0 Figure 5 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE -10.0 -20.0 -15.0 -30.0 -20.0 TA = 85?C TA = 25?C 0.5 1.0 1.5 2.0 2.5 VOH - High-Level Output Voltage - V -40.0 TA = 85?C -25.0 0.0 -50.0 0.0 TA = 25?C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH - High-Level Output Voltage - V Figure 6 NOTE: One output loaded at a time. Figure 7 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 29 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Notes 1 and 2) PARAMETER VCC(start) V(B_IT-) Vhys(B_IT-) td(BOR) t(reset) (see Figure 8) (see Figure 8 through Figure 10) (see Figure 8) (see Figure 8) Pulse length needed at RST/NMI pin to accepted reset internally 2.2 V/3 V 2 TEST CONDITIONS dVCC/dt 3 V/s dVCC/dt 3 V/s dVCC/dt 3 V/s VCC MIN TYP MAX 1.71 70 130 210 2000 UNIT V V mV ?s ?s 0.7 ? V(B_IT-) NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT-) is 1.8V. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. VCC Vhys(B_IT-) V(B_IT-) VCC(start) 1 0 t d(BOR) Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage 30 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics - POR/brownout reset (BOR) 2 VCC = 3 V Typical Conditions VCC(drop) - V 1.5 1 0.5 0 0.001 VCC(drop) VCC 3V t pw 1 tpw - Pulse Width - ?s 1000 1 ns 1 ns tpw - Pulse Width - ?s Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 VCC(drop) - V 1.5 1 VCC(drop) 0.5 0 0.001 tf = tr 1 tpw - Pulse Width - ?s 1000 tf tr tpw - Pulse Width - ?s VCC = 3 V Typical Conditions 3V t pw Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 31 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. D DCO control bits DCOx have a step size as defined by parameter SDCO. D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: f average + DCO frequency PARAMETER TEST CONDITIONS RSELx < 14 Vcc fDCO(0,0) fDCO(0,3) fDCO(1,3) fDCO(2,3) fDCO(3,3) fDCO(4,3) fDCO(5,3) fDCO(6,3) fDCO(7,3) fDCO(8,3) fDCO(9,3) fDCO(10,3) fDCO(11,3) fDCO(12,3) fDCO(13,3) fDCO(14,3) fDCO(15,3) fDCO(15,7) SRSEL SDCO Duty Cycle Supply voltage range DCO frequency (0, 0) DCO frequency (0, 3) DCO frequency (1, 3) DCO frequency (2, 3) DCO frequency (3, 3) DCO frequency (4, 3) DCO frequency (5, 3) DCO frequency (6, 3) DCO frequency (7, 3) DCO frequency (8, 3) DCO frequency (9, 3) DCO frequency (10, 3) DCO frequency (11, 3) DCO frequency (12, 3) DCO frequency (13, 3) DCO frequency (14, 3) DCO frequency (15, 3) DCO frequency (15, 7) Frequency step between range RSEL and RSEL+1 Frequency step between tap DCO and DCO+1 RSELx = 14 RSELx = 15 RSELx = 0, DCOx = 0, MODx = 0 RSELx = 0, DCOx = 3, MODx = 0 RSELx = 1, DCOx = 3, MODx = 0 RSELx = 2, DCOx = 3, MODx = 0 RSELx = 3, DCOx = 3, MODx = 0 RSELx = 4, DCOx = 3, MODx = 0 RSELx = 5, DCOx = 3, MODx = 0 RSELx = 6, DCOx = 3, MODx = 0 RSELx = 7, DCOx = 3, MODx = 0 RSELx = 8, DCOx = 3, MODx = 0 RSELx = 9, DCOx = 3, MODx = 0 RSELx = 10, DCOx = 3, MODx = 0 RSELx = 11, DCOx = 3, MODx = 0 RSELx = 12, DCOx = 3, MODx = 0 RSELx = 13, DCOx = 3, MODx = 0 RSELx = 14, DCOx = 3, MODx = 0 RSELx = 15, DCOx = 3, MODx = 0 RSELx = 15, DCOx = 7, MODx = 0 SRSEL f = DCO(RSEL+1,DCO)/fDCO(RSEL,DCO) SDCO f= DCO(RSEL,DCO+1)/fDCO(RSEL,DCO) Measured at P1.4/SMCLK 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 3V 3V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 1.05 40 1.08 50 VCC MIN 1.8 2.2 3.0 0.06 0.07 0.10 0.14 0.20 0.28 0.39 0.54 0.80 1.10 1.60 2.50 3.00 4.30 6.00 8.60 12.0 16.0 TYP MAX 3.6 3.6 3.6 0.14 0.17 0.20 0.28 0.40 0.54 0.77 1.06 1.50 2.10 3.00 4.30 5.50 7.30 9.60 13.9 18.5 26.0 1.55 ratio 1.12 60 % UNIT V V V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MOD 32 f DCO(RSEL,DCO) f DCO(RSEL,DCO)1) f DCO(RSEL,DCO))(32*MOD) f DCO(RSEL,DCO)1) 32 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) calibrated DCO frequencies - tolerance at calibration PARAMETER Frequency tolerance at calibration fCAL(1MHz) 1MHz calibration value BCSCTL1= CALBC1_1MHZ DCOCTL = CALDCO_1MHZ Gating time: 5ms BCSCTL1= CALBC1_8MHZ DCOCTL = CALDCO_8MHZ Gating time: 5ms BCSCTL1= CALBC1_12MHZ DCOCTL = CALDCO_12MHZ Gating time: 5ms BCSCTL1= CALBC1_16MHZ DCOCTL = CALDCO_16MHZ Gating time: 2ms TEST CONDITIONS TA 25?C 25?C VCC 3V 3V MIN -1 0.990 TYP ?0.2 1 MAX +1 1.010 UNIT % MHz fCAL(8MHz) 8MHz calibration value 25?C 3V 7.920 8 8.080 MHz fCAL(12MHz) 12MHz calibration value 25?C 3V 11.88 12 12.12 MHz fCAL(16MHz) 16MHz calibration value 25?C 3V 15.84 16 16.16 MHz calibrated DCO frequencies - tolerance over temperature 0?C to +85?C PARAMETER 1 MHz tolerance over temperature 8 MHz tolerance over temperature 12 MHz tolerance over temperature 16 MHz tolerance over temperature BCSCTL1= CALBC1_1MHZ DCOCTL = CALDCO_1MHZ Gating time: 5ms BCSCTL1= CALBC1_8MHZ DCOCTL = CALDCO_8MHZ Gating time: 5ms BCSCTL1= CALBC1_12MHZ DCOCTL = CALDCO_12MHZ Gating time: 5ms BCSCTL1= CALBC1_16MHZ DCOCTL = CALDCO_16MHZ Gating time: 2ms TEST CONDITIONS TA 0-85?C 0-85?C 0-85?C 0-85?C VCC 3.0 V 3.0 V 3.0 V 3.0 V 2.2 V 0-85 C 0-85?C 3.0 V 3.6 V 2.2 V 0-85 C 0-85?C 3.0 V 3.6 V 2.2 V 0-85 C 0-85?C 3.0 V 3.6 V 3.0 V 0-85?C 3.6 V 15.00 16 16.48 MHz MIN -2.5 -2.5 -2.5 -3.0 0.970 0.975 0.970 7.760 7.800 7.600 11.70 11.70 11.70 15.52 TYP ?0.5 ?1.0 ?1.0 ?2.0 1 1 1 8 8 8 12 12 12 16 MAX +2.5 +2.5 +2.5 +3.0 1.030 1.025 1.030 8.400 8.200 8.240 12.30 12.30 12.30 16.48 UNIT % % % % MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz fCAL(1MHz) 1MHz calibration value fCAL(8MHz) 8MHz calibration value fCAL(12MHz) 12MHz calibration value fCAL(16MHz) 16MHz calibration value POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 33 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) calibrated DCO frequencies - tolerance over supply voltage VCC PARAMETER 1 MHz tolerance over VCC 8 MHz tolerance over VCC 12 MHz tolerance over VCC 16 MHz tolerance over VCC fCAL(1MHz) 1MHz calibration value BCSCTL1= CALBC1_1MHZ DCOCTL = CALDCO_1MHZ Gating time: 5ms BCSCTL1= CALBC1_8MHZ DCOCTL = CALDCO_8MHZ Gating time: 5ms BCSCTL1= CALBC1_12MHZ DCOCTL = CALDCO_12MHZ Gating time: 5ms BCSCTL1= CALBC1_16MHZ DCOCTL = CALDCO_16MHZ Gating time: 2ms TEST CONDITIONS TA 25?C 25?C 25?C 25?C 25?C VCC 1.8 V - 3.6 V 1.8 V - 3.6 V 2.2 V - 3.6 V 3.0 V - 3.6 V 1.8 V - 3.6 V MIN -3 -3 -3 -6 0.970 TYP ?2 ?2 ?2 ?2 1 MAX +3 +3 +3 +3 1.030 UNIT % % % % MHz fCAL(8MHz) 8MHz calibration value 25?C 1.8 V - 3.6 V 7.760 8 8.240 MHz fCAL(12MHz) 12MHz calibration value 25?C 2.2 V - 3.6 V 11.64 12 12.36 MHz fCAL(16MHz) 16MHz calibration value 25?C 3.0 V - 3.6 V 15.00 16 16.48 MHz calibrated DCO frequencies - overall tolerance PARAMETER 1 MHz tolerance overall 8 MHz tolerance overall 12 MHz tolerance overall 16 MHz tolerance overall BCSCTL1= CALBC1_1MHZ DCOCTL = CALDCO_1MHZ Gating time: 5ms BCSCTL1= CALBC1_8MHZ DCOCTL = CALDCO_8MHZ Gating time: 5ms BCSCTL1= CALBC1_12MHZ DCOCTL = CALDCO_12MHZ Gating time: 5ms BCSCTL1= CALBC1_16MHZ DCOCTL = CALDCO_16MHZ Gating time: 2ms TEST CONDITIONS TA I: -40-85?C T: -40-105?C I: -40-85?C T: -40-105?C I: -40-85?C T: -40-105?C I: -40-85?C T: -40-105?C I: -40-85?C T: -40-105?C I: -40-85?C T: -40-105?C I: -40-85?C T: -40-105?C I: -40-85?C T: -40-105?C VCC 1.8 V - 3.6 V 1.8 V - 3.6 V 2.2 V - 3.6 V 3.0 V - 3.6 V MIN -5 -5 -5 -6 TYP ?2 ?2 ?2 ?3 MAX +5 +5 +5 +6 UNIT % % % % fCAL(1MHz) 1MHz calibration value 1.8 V - 3.6 V 0.950 1 1.050 MHz fCAL(8MHz) 8MHz calibration value 1.8 V - 3.6 V 7.600 8 8.400 MHz fCAL(12MHz) 12MHz calibration value 2.2 V - 3.6 V 11.40 12 12.60 MHz fCAL(16MHz) 16MHz calibration value 3.0 V - 3.6 V 15.00 16 17.00 MHz 34 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 typical characteristics - calibrated 1MHz DCO frequency 1.03 1.02 VCC = 1.8 V 1.01 Frequency - MHz 1.00 VCC = 2.2 V VCC = 3.0 V 0.99 VCC = 3.6 V 0.98 0.97 -50.0 -25.0 0.0 25.0 50.0 75.0 100.0 TA - Temperature - ?C Figure 11. Calibrated 1 MHz Frequency vs. Temperature 1.03 1.02 Frequency - MHz 1.01 TA = 105 ?C TA = 85 ?C TA = 25 ?C 1.00 0.99 TA = -40 ?C 0.98 0.97 1.5 2.0 2.5 3.0 3.5 4.0 VCC - Supply Voltage - V Figure 12. Calibrated 1 MHz Frequency vs. VCC POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 35 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) wake-up from lower power modes (LPM3/4) PARAMETER TEST CONDITIONS BCSCTL1= CALBC1_1MHZ DCOCTL = CALDCO_1MHZ DCO clock wake-up time from tDCO,LPM3/4 LPM3/4 (see Note 1) BCSCTL1= CALBC1_8MHZ DCOCTL = CALDCO_8MHZ BCSCTL1= CALBC1_12MHZ DCOCTL = CALDCO_12MHZ BCSCTL1= CALBC1_16MHZ DCOCTL = CALDCO_16MHZ tCPU,LPM3/4 CPU wake-up time from LPM3/4 (see Note 2) VCC 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 3V MIN TYP MAX 2 1.5 s ?s 1 1 UNIT 1/fMCLK + tClock,LPM3/4 NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). 2. Parameter applicable only if DCOCLK is used for MCLK. typical characteristics - DCO clock wake-up time from LPM3/4 10.00 DCO Wake Time - us RSELx = 0...11 1.00 RSELx = 12...15 0.10 0.10 1.00 DCO Frequency - MHz 10.00 Figure 13. Clock wake-up time from LPM3 vs DCO frequency 36 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) DCO with external resistor ROSC (see Note 1) PARAMETER fDCO,ROSC Dt DV DCO output frequency with ROSC Temperature drift Drift with VCC TEST CONDITIONS DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, TA = 25?C DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 VCC 2.2 V 3V 2.2 V/3 V 2.2 V/3 V MIN TYP 1.8 MHz 1.95 ?0.1 10 %/?C %/V MAX UNIT NOTES: 1. ROSC = 100k. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ?50ppm/?C. typical characteristics - DCO with external resistor ROSC 10.00 10.00 DCO Frequency - MHz 1.00 DCO Frequency - MHz 1.00 0.10 RSELx = 4 0.10 RSELx = 4 0.01 10.00 100.00 1000.00 10000.00 0.01 10.00 100.00 1000.00 10000.00 ROSC - External Resistor - kOhm ROSC - External Resistor - kOhm Figure 14. DCO Frequency vs ROSC, VCC = 2.2 V, TA = 255C 2.50 2.25 2.00 1.75 DCO Frequency - MHz 1.50 1.25 1.00 0.75 0.50 0.25 0.00 -50.0 -25.0 0.0 25.0 ROSC = 1M ROSC = 270k DCO Frequency - MHz ROSC = 100k 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 100.0 Figure 15. DCO Frequency vs ROSC, VCC = 3.0 V, TA = 255C ROSC = 100k ROSC = 270k ROSC = 1M 50.0 75.0 0.00 2.0 2.5 3.0 3.5 4.0 TA - Temperature - 5C VCC - Supply Voltage - V Figure 16. DCO Frequency vs Temperature, VCC = 3.0 V Figure 17. DCO Frequency vs VCC, TA = 255C POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 37 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1, low frequency modes (see Note 4) PARAMETER fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 TEST CONDITIONS XTS = 0, LFXT1Sx = 0 or 1 VCC 1.8 V - 3.6 V MIN TYP 32,768 MAX UNIT Hz LFXT1 oscillator logic level fLFXT1,LF,logic square wave input frequency, LF mode XTS = 0, LFXT1Sx = 3 XTS = 0, LFXT1Sx = 0; fLFXT1,LF = 32,768 kHz, CL,eff = 6 pF XTS = 0, LFXT1Sx = 0; fLFXT1,LF = 32,768 kHz, CL,eff = 12 pF XTS = 0, XCAPx = 0 XTS = 0, XCAPx = 1 XTS = 0, XCAPx = 2 XTS = 0, XCAPx = 3 XTS = 0, Measured at P1.4/ACLK, fLFXT1,LF = 32,768 Hz XTS = 0, LFXT1Sx = 3 (see Notes 2) 1.8 V - 3.6 V 10,000 32,768 50,000 Hz 500 kW OALF Oscillation Allowance for LF crystals 200 1 5.5 8.5 11 2.2 V/3 V 30 50 70 kW pF pF pF pF % CL,eff Integrated effective Load Capacitance, LF mode (see Note 1) Duty Cycle LF mode Oscillator fault frequency, LF mode (see Note 3) fFault,LF 2.2 V/3 V 10 10,000 Hz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Measured with logic level input frequency but also applies to operation with crystals. 3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed. - Keep as short a trace as possible between the device and the crystal. - Design a good ground plane around the oscillator pins. - Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. - Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. - Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. - If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. - Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. internal very low power, low frequency oscillator (VLO) PARAMETER fVLO dfVLO/dT dfVLO/dVCC VLO frequency VLO frequency temperature drift VLO frequency supply voltage drift (see Note 1) (see Note 2) TEST CONDITIONS TA -40-85?C 105?C I: -40-85?C T: -40-105?C 25?C VCC 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 1.8V - 3.6V 0.5 4 MIN 4 TYP 12 MAX 20 22 kHz %/?C %/V UNIT NOTES: 1. Calculated using the box method: I Version: (MAX(-40...85_C) - MIN(-40...85_C))/MIN(-40...85_C)/(85_C - (-40_C)) T Version: (MAX(-40...105_C) - MIN(-40...105_C))/MIN(-40...105_C)/(105_C - (-40_C)) 2. Calculated using the box method: (MAX(1.8...3.6V) - MIN(1.8...3.6V))/MIN(1.8...3.6V)/(3.6V - 1.8V) 38 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1, high frequency modes (see Note 5) PARAMETER fLFXT1,HF0 fLFXT1,HF1 LFXT1 oscillator crystal frequency, HF mode 0 LFXT1 oscillator crystal frequency, HF mode 1 LFXT1 oscillator crystal frequency, HF mode 2 TEST CONDITIONS XTS = 1, LFXT1Sx = 0 XTS = 1, LFXT1Sx = 1 VCC 1.8 V - 3.6 V 1.8 V - 3.6 V 1.8 V - 3.6 V fLFXT1,HF2 XTS = 1, LFXT1Sx = 2 2.2 V - 3.6 V 3.0 V - 3.6 V LFXT1 oscillator logic level square fLFXT1,HF,logic wave input frequency, HF mode 1.8 V - 3.6 V XTS = 1, LFXT1Sx = 3 XTS = 0, LFXT1Sx = 0, fLFXT1,HF = 1 MHz, CL,eff = 15 pF OAHF Oscillation Allowance for HF crystals (refer to Figure 18 and Figure 19) XTS = 0, LFXT1Sx = 1 fLFXT1,HF = 4 MHz, CL,eff = 15 pF XTS = 0, LFXT1Sx = 2 fLFXT1,HF = 16 MHz, CL,eff = 15 pF XTS = 1 (see Note 2) XTS = 1, Measured at P1.4/ACLK, fLFXT1,HF = 10 MHz XTS = 1, Measured at P1.4/ACLK, fLFXT1,HF = 16 MHz XTS = 1, LFXT1Sx = 3 (see Notes 3) 2.2 V - 3.6 V 3.0 V - 3.6 V MIN 0.4 1 2 2 2 0.4 0.4 0.4 2700 TYP MAX 1 4 10 12 16 10 12 16 UNIT MHz MHz MHz MHz MHz MHz MHz MHz W 800 W 300 W CL,eff Integrated effective Load Capacitance, HF mode (see Note 1) 1 pF 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 40 40 30 50 50 60 60 300 % % kHz Duty Cycle HF mode fFault,HF Oscillator fault frequency, HF mode (see Note 4) NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 3. Measured with logic level input frequency but also applies to operation with crystals. 4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed. - Keep as short a trace as possible between the device and the crystal. - Design a good ground plane around the oscillator pins. - Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. - Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. - Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. - If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. - Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 39 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics - LFXT1 oscillator in HF mode (XTS = 1) 100000.00 Oscillation Allowance - Ohms 10000.00 1000.00 LFXT1Sx = 3 100.00 LFXT1Sx = 1 LFXT1Sx = 2 10.00 0.10 1.00 10.00 100.00 Crystal Frequency - MHz Figure 18. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25?C 800.0 LFXT1Sx = 3 XT Oscillator Supply Current - uA 700.0 600.0 500.0 400.0 300.0 200.0 100.0 LFXT1Sx = 1 0.0 0.0 4.0 8.0 12.0 16.0 20.0 LFXT1Sx = 2 Crystal Frequency - MHz Figure 19. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25?C 40 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Timer_A PARAMETER fTA tTA,cap Timer_A clock frequency Timer_A, capture timing TEST CONDITIONS Internal: SMCLK, ACLK; External: TACLK, INCLK; Duty Cycle = 50% ?10% TA0, TA1, TA2 VCC 2.2 V 3V 2.2 V/3 V 20 MIN TYP MAX 10 MHz 16 ns UNIT Timer_B PARAMETER fTB tTB,cap Timer_B clock frequency Timer_B, capture timing TEST CONDITIONS Internal: SMCLK, ACLK; External: TBCLK; Duty Cycle = 50% ?10% TB0, TB1, TB2 VCC 2.2 V 3V 2.2 V/3 V 20 MIN TYP MAX 10 MHz 16 ns UNIT POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 41 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (UART Mode) PARAMETER fUSCI fBITCLK t USCI input clock frequency BITCLK clock frequency (equals Baudrate in MBaud) UART receive deglitch time (see Note 1) TEST CONDITIONS Internal: SMCLK, ACLK External: UCLK Duty Cycle = 50% ? 10% 2.2V /3 V 2.2 V 3V 50 50 150 100 VCC MIN TYP MAX UNIT MHz fSYSTEM 1 600 600 MHz ns ns NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. USCI (SPI Master Mode, see Figure 20 and Figure 21) PARAMETER fUSCI tSU,MI tHD,MI tVALID,MO USCI input clock frequency SOMI input data setup time SOMI input data hold time SIMO output data valid time UCLK edge to SIMO valid; CL = 20 pF TEST CONDITIONS SMCLK, ACLK Duty Cycle = 50% ? 10% 2.2 V 3V 2.2 V 3V 2.2 V 3V 110 75 0 0 30 20 VCC MIN TYP MAX UNIT MHz ns ns ns ns ns ns fSYSTEM USCI (SPI Slave Mode, see Figure 22 and Figure 23) PARAMETER tSTE,LEAD tSTE,LAG tSTE,ACC tSTE,DIS tSU,SI tHD,SI tVALID,SO STE lead time STE low to clock STE lag time Last clock to STE high STE access time STE low to SOMI data out STE disable time STE high to SOMI high impedance SIMO input data setup time SIMO input data hold time SOMI output data valid time UCLK edge to SOMI valid; CL = 20 pF TEST CONDITIONS VCC 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V 3V 2.2 V 3V 2.2 V 3V 20 15 10 10 75 50 110 75 10 50 50 MIN TYP 50 MAX UNIT ns ns ns ns ns ns ns ns ns ns 42 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 1/fUCxCLK CKPL UCLK CKPL =1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI =0 tVALID ,MO SIMO Figure 20. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL UCLK CKPL =1 tLOW/HIGH tLOW/HIGH tSU,MI SOMI tHD,MI =0 tVALID ,MO SIMO Figure 21. SPI Master Mode, CKPH = 1 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 43 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) tSTE,LEAD STE 1/fUCxCLK CKPL UCLK CKPL =1 tLOW/HIGH tLOW/HIGH tSU,SIMO tHD,SIMO SIMO =0 tSTE,LAG tACC SOMI tVALID ,SOMI tDIS Figure 22. SPI Slave Mode, CKPH = 0 tSTE,LEAD STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLOW/HIGH tLOW/HIGH tSU,SI SIMO tHD,SI tSTE,LAG tACC SOMI tVALID ,SO tDIS Figure 23. SPI Slave Mode, CKPH = 1 44 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (I2C Mode, see Figure 24) PARAMETER fUSCI fSCL tHD,STA tSU,STA tHD,DAT tSU,DAT tSU,STO tSP USCI input clock frequency SCL clock frequency Hold time (repeated) START Set-up time for a repeated START Data hold time Data set-up time Set-up time for STOP Pulse width of spikes suppressed by input filter tHD , STA SDA TEST CONDITIONS Internal: SMCLK, ACLK External: UCLK Duty Cycle = 50% ? 10% VCC MIN TYP MAX UNIT MHz kHz us us us us ns ns us fSYSTEM 2.2 V/3 V 0 4.0 0.6 4.7 0.6 0 250 4.0 50 50 150 100 tBUF 600 600 400 fSCL 100kHz fSCL > 100kHz fSCL 100kHz fSCL > 100kHz 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V 3V tSU , STA tHD , STA ns ns t SCL LOW tHIGH tSP tSU ,DAT tHD ,DAT tSU , STO Figure 24. I2C Mode Timing POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 45 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, power supply and input range conditions (see Note 1) PARAMETER VCC VAx Analog supply voltage range Analog input voltage range (see Note 2) TEST CONDITIONS VSS = 0 V All Ax terminals. Analog inputs selected in ADC10AE register. fADC10CLK = 5.0 MHz ADC10ON = 1, REFON = 0 ADC10SHT0 = 1, ADC10SHT1 = 0, ADC10DIV =0 fADC10CLK = 5.0 MHz ADC10ON = 0, REF2_5V = 0, REFON = 1, REFOUT = 0 fADC10CLK = 5.0 MHz ADC10ON = 0, REF2_5V = 1, REFON = 1, REFOUT = 0 fADC10CLK = 5.0 MHz ADC10ON = 0, REFON = 1, REF2_5V = 0, REFOUT = 1, ADC10SR=0 fADC10CLK = 5.0 MHz ADC10ON = 0, REFON = 1, REF2_5V = 0, REFOUT = 1, ADC10SR=1 Only one terminal Ax selected at a time 0V VAx VCC 2.2 V I: -40-85?C -40-85 C T: -40-105?C 3V I: -40-85?C T: -40-105?C I: -40-85?C T: -40-105?C -40-85?C 105?C 0.6 1.2 TA VCC MIN 2.2 TYP MAX 3.6 UNIT V 0 VCC V 0.52 1.05 mA IADC10 ADC10 supply current (see Note 3) IREF+ Reference supply current, reference buffer disabled (see Note 4) 2.2 V/3 V 0.25 3V 0.4 mA mA IREFB,0 Reference buffer supply current with ADC10SR=0 (see Note 4) 2.2 V/3 V 2.2 V/3 V 1.1 1.4 1.8 mA mA IREFB,1 Reference buffer supply current with ADC10SR=1 (see Note 4) -40-85?C 2.2 V/3 V 0.5 0.7 mA 105?C I: -40-85?C T: -40-105?C I: -40-85?C T: -40-105?C 2.2 V/3 V 0.8 mA CI RI NOTES: 1. 2. 3. 4. Input capacitance Input MUX ON resistance 27 2.2 V/3 V 2000 pF The leakage current is defined in the leakage current table with Px.x/Ax parameter. The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results. The internal reference supply current is not included in current consumption parameter IADC10. The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion. 46 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, built-in voltage reference PARAMETER Positive built-in reference analog supply voltage range TEST CONDITIONS IVREF+ 1mA, REF2_5V=0 IVREF+ 0.5mA, REF2_5V=1 IVREF+ 1mA, REF2_5V=1 IVREF+ IVREF+max, REF2_5V=0 IVREF+ IVREF+max, REF2_5V=1 2.2 V/3 V 3V 2.2 V ILD,VREF+ Maximum VREF+ load current IVREF+ = 500 ?A ? 100 ?A Analog input voltage VAx 0.75 V; REF2_5V=0 VREF+ load regulation IVREF+ = 500 ?A ? 100 ?A Analog input voltage VAx 1.25 V; REF2_5V=1 IVREF+ = 100?A900?A, VAx 0.5 x VREF+ Error of conversion result 1 LSB ADC10SR=0 ADC10SR=1 3V 2.2 V/3 V VCC MIN 2.2 2.8 2.9 1.41 2.35 1.5 2.5 1.59 2.65 ?0.5 ?1 ?2 V V mA V TYP MAX UNIT VCC,REF+ VREF+ Positive built-in reference voltage LSB 3V ?2 LSB 3V 3V 2.2 V/3 V 2.2 V/3 V 3.6 V 2.2 V 2.2 V 3V 3V 400 ns 2000 100 pF VREF+ load regulation response time CVREF+ TCREF+ tREFON Max. capacitance at pin VREF+ (see Note 1) Temperature coefficient Settling time of internal reference voltage (see Note 2) IVREF+ ?1mA, REFON=1, REFOUT=1 IVREF+ = const. with 0 mA IVREF+ 1 mA IVREF+ = 0.5 mA, REF2_5V=0 REFON = 0 1 IVREF+ = 0.5 mA, REF2_5V=0, REFON = 1, REFBURST = 1 IVREF+ = 0.5 mA, REF2_5V=1, REFON = 1, REFBURST = 1 ADC10SR=0 ADC10SR=1 ADC10SR=0 ADC10SR=1 ?100 ppm/?C 30 1 ?s s 2.5 2 s ?s 4.5 ?s tREFBURST Settling time of reference buffer (see Note 2) NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT=1), must be limited; the reference buffer may become unstable otherwise. 2. The condition is that the error in a conversion started after tREFON or tRefBuf is less than ?0.5 LSB. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 47 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, external reference (see Note 1) PARAMETER Positive external reference input voltage range (see Note 2) Negative external reference input voltage range (see Note 4) Differential external reference input voltage range VeREF = VeREF+ - VeREF- TEST CONDITIONS VeREF+ > VeREF- SREF1 = 1, SREF0 = 0 VeREF- VeREF+ VCC - 0.15V SREF1 = 1, SREF0 = 1 (see Note 3) VeREF+ > VeREF- VeREF+ > VeREF- (see Note 5) 0V VeREF+ VCC, SREF1 = 1, SREF0 = 0 IVeREF+ Static input current into VeREF+ 0V VeREF+ VCC - 0.15V 3V SREF1 = 1, SREF0 = 1 (see Note 3) 2.2 V/3 V 2.2 V/3 V VCC MIN 1.4 1.4 0 TYP MAX VCC 3.0 1.2 UNIT V V V VeREF+ VeREF- VeREF 1.4 VCC ?1 0 V ?A ?A IVeREF- Static input current into VeREF- 0V VeREF- VCC 2.2 V/3 V ?1 ?A NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1. 4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. 48 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, timing parameters PARAMETER TEST CONDITIONS For specified performance of ADC10 linearity parameters ADC10SR=0 ADC10SR=1 VCC 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V MIN 0.45 0.45 3.7 TYP MAX 6.3 MHz 1.5 6.3 MHz ?s UNIT fADC10CLK ADC10 input clock frequency fADC10OSC ADC10 built-in oscillator frequency ADC10DIVx=0, ADC10SSELx = 0 fADC10CLK = fADC10OSC ADC10 built-in oscillator, ADC10SSELx = 0 fADC10CLK = fADC10OSC fADC10CLK from ACLK, MCLK or SMCLK: ADC10SSELx 0 2.2 V/3 V 2.06 13? ADC10DIV? 1/fADC10CLK 3.51 tCONVERT Conversion time ?s tADC10ON Turn on settling time of the ADC (see Note 1) 100 ns NOTES: 1. The condition is that the error in a conversion started after tADC10ON is less than ?0.5 LSB. The reference and input signal are already settled. 10-bit ADC, linearity parameters PARAMETER EI ED EO Integral linearity error Differential linearity error Offset error Source impedance RS < 100 , SREFx = 010; un-buffered external reference; VeREF+ = 1.5V SREFx = 010; un-buffered external reference; VeREF+ = 2.5V EG Gain error SREFx = 011; buffered external reference (see Note 1); VeREF+ = 1.5V SREFx = 011; buffered external reference (see Note 1); VeREF+ = 2.5V SREFx = 010; un-buffered external reference; VeREF+ = 1.5V SREFx = 010; un-buffered external reference; VeREF+ = 2.5V ET Total unadjusted error SREFx = 011; buffered external reference (see Note 1); VeREF+ = 1.5V SREFx = 011; buffered external reference (see Note 1); VeREF+ = 2.5V NOTES: 1. The reference buffer's offset adds to the gain and total unadjusted error. TEST CONDITIONS VCC 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V 3V ?1.1 ?1.1 ?1.1 MIN TYP MAX ?1 ?1 ?1 ?2 ?2 ?4 UNIT LSB LSB LSB LSB LSB 2.2 V LSB 3V ?1.1 ?2 ?2 ?2 ?3 ?5 ?5 ?7 LSB 2.2 V 3V LSB LSB 2.2 V LSB 3V ?2 ?6 LSB POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 49 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, temperature sensor and built-in VMID PARAMETER ISENSOR TCSENSOR VOffset,Sensor Sensor offset voltage Temperature sensor supply current (see Note 1) TEST CONDITIONS REFON = 0, INCHx = 0Ah, TA = 25_C ADC10ON = 1, INCHx = 0Ah (see Note 2) ADC10ON = 1, INCHx = 0Ah (see Note 2) Temperature sensor voltage at TA = 105?C (T Version only) Sensor output voltage (see Note 3) Temperature sensor voltage at TA = 85?C Temperature sensor voltage at TA = 25?C Temperature sensor voltage at TA = 0?C Sample time required if tSensor(sample) channel 10 is selected (see Note 4) IVMID VMID Current into divider at channel 11 (see Note 5) VCC divider at channel 11 ADC10ON = 1, INCHx = 0Ah, Error of conversion result 1 LSB ADC10ON = 1, INCHx = 0Bh, ADC10ON = 1, INCHx = 0Bh, VMID is 0.5 x VCC ADC10ON = 1, INCHx = 0Bh, Error of conversion result 1 LSB 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V VCC 2.2 V 3V 2.2 V/3 V 3.44 -100 1265 1195 985 895 1365 1295 1085 995 MIN TYP 40 60 3.55 MAX 120 160 3.66 100 1465 1395 1185 mV 1095 ?s NA NA 1.06 1.46 1400 ns 3V 1220 1.1 1.5 1.14 1.54 V UNIT ?A A mV/?C mV mV mV VSensor 2.2 V/3 V 2.2 V 3V 2.2 V 3V 2.2 V 30 A ?A Sample time required if tVMID(sample) channel 11 is selected (see Note 6) NOTES: 1. The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor input (INCH = 0Ah). 2. The following formula can be used to calculate the temperature sensor output voltage: VSensor,typ = TCSensor ( 273 + T [?C] ) + VOffset,sensor [mV] or VSensor,typ = TCSensor T [?C] + VSensor(TA = 0?C) [mV] 3. Results based on characterization and/or production test, not TCSensor or VOffset,sensor. 4. The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on). 5. No additional current is needed. The VMID is used during sampling. 6. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. 50 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) operational amplifier OA, supply specifications (MSP430x22x4 only) PARAMETER VCC ICC PSRR Supply voltage range Fast Mode Supply current (see Note 1) Power supply rejection ratio Medium Mode Slow Mode Non-inverting NOTES: 1. Corresponding pins configured as OA inputs and outputs respectively. 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V TEST CONDITIONS VCC MIN 2.2 180 110 50 70 TYP MAX 3.6 290 190 80 dB ?A UNIT V operational amplifier OA, input/output specifications (MSP430x22x4 only) PARAMETER VI/P IIkg Input voltage range Input leakage current (see Notes 1 and 2) TA = -40 to +55_C TA = +55 to +85_C TA = +85 to +105_C Fast Mode Medium Mode Slow Mode Vn Voltage noise density, I/P Fast Mode Medium Mode Slow Mode VIO Offset voltage, I/P Offset temperature drift, I/P Offset voltage drift with supply, I/P VOH VOL High-level output voltage, O/P Low-level output voltage, O/P see Note 3 0.3V VIN VCC-1.0V VCC ? 10%, TA = 25?C Fast Mode, ISOURCE -500?A Slow Mode,ISOURCE -150?A Fast Mode, ISOURCE +500?A Slow Mode,ISOURCE +150?A RLoad= 3 k, CLoad = 50pF, VO/P(OAx) < 0.2 V RO/P(OAx) Output Resistance (see Figure 25 and Note 4) RLoad= 3 k, CLoad = 50pF, VO/P(OAx) > VCC - 1.2 V RLoad= 3 k, CLoad = 50pF, 0.2 V VO/P(OAx) VCC - 0.2 V CMRR NOTES: 1. 2. 3. 4. Common-mode rejection ratio Non-inverting ESD damage can degrade input current leakage. The input bias current is overridden by the input leakage current. Calculated using the box method. Specification valid for voltage-follower OAx configuration. 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V VCC-0.2 VCC-0.1 VSS VSS 150 150 0.1 70 ?10 ?1.5 VCC VCC 0.2 0.1 250 250 4 dB V fV(I/P) = 10 kHz fV(I/P) = 1 kHz 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V TEST CONDITIONS VCC MIN -0.1 -5 -20 -50 50 80 140 30 50 65 ?10 mV ?V/?C mV/V V nV/Hz ?0.5 ?5 TYP MAX VCC-1.2 5 20 50 UNIT V nA nA nA POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 51 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) RO/P(OAx) ILoad OAx O/P(OAx) CLoad RLoad AV CC 2 Min 0.2V AV CC -0.2VAV V CC OUT Max Figure 25. OAx Output Resistance Tests operational amplifier OA, dynamic specifications (MSP430x22x4 only) PARAMETER TEST CONDITIONS Fast Mode SR Slew rate Open-loop voltage gain m Phase margin Gain margin CL = 50 pF CL = 50 pF Non-inverting, Fast Mode, RL = 47k, CL = 50pF GBW Gain-Bandwidth Product (see Figure 26 and Figure 27) Non-inverting, Medium Mode, RL =300k, CL = 50pF Non-inverting, Slow Mode, RL =300k, CL = 50pF ten(on) ten(off) Enable time on Enable time off ton, non-inverting, Gain = 1 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V Medium Mode Slow Mode VCC MIN TYP 1.2 0.8 0.3 100 60 20 2.2 1.4 0.5 10 20 1 ?s ?s MHz dB deg dB V/?s MAX UNIT TYPICAL OPEN-LOOP GAIN vs FREQUENCY 140 120 100 80 Fast Mode Gain - dB 60 40 Medium Mode 20 0 Slow Mode -20 -40 -60 -80 1 10 100 1000 10000 100000 Input Frequency - kHz -250 1 -200 Phase - degrees -100 -50 0 TYPICAL PHASE vs FREQUENCY Fast Mode Medium Mode -150 Slow Mode 10 100 1000 10000 100000 Input Frequency - kHz Figure 26 Figure 27 52 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) operational amplifier OA feedback network, resistor network (see Note 1. MSP430x22x4 only) PARAMETER Rtotal Runit Total resistance of resistor string Unit resistor of resistor string (see Note 2) TEST CONDITIONS VCC MIN 76 4.8 TYP 96 6 MAX 128 8 UNIT k k NOTES: 1. A single resistor string is composed of 4 Runit + 4 Runit + 2 Runit + 2 Runit + 1 Runit + 1 Runit + 1 Runit + 1 Runit = 16 Runit = Rtotal. 2. For the matching (i.e. the relative accuracy) of the unit resistors on a device refer to the gain and level specifications of the respective configurations. operational amplifier OA feedback network, comparator mode (OAFCx = 3. MSP430x22x4 only) PARAMETER TEST CONDITIONS OAFBRx = 1, OARRIP = 0 OAFBRx = 2, OARRIP = 0 OAFBRx = 3, OARRIP = 0 OAFBRx = 4, OARRIP = 0 OAFBRx = 5, OARRIP = 0 OAFBRx = 6, OARRIP = 0 OAFBRx = 7, OARRIP = 0 VLevel Comparator level OAFBRx = 1, OARRIP = 1 OAFBRx = 2, OARRIP = 1 OAFBRx = 3, OARRIP = 1 OAFBRx = 4, OARRIP = 1 OAFBRx = 5, OARRIP = 1 OAFBRx = 6, OARRIP = 1 OAFBRx = 7, OARRIP = 1 Fast Mode, Overdrive 10mV Fast Mode, Overdrive 100mV Fast Mode, Overdrive 500mV Medium Mode, Overdrive 10mV tPLH, tPHL Propagation delay (low-high and high-low) Medium Mode, Overdrive 100mV Medium Mode, Overdrive 500mV Slow Mode, Overdrive 10mV Slow Mode, Overdrive 100mV Slow Mode, Overdrive 500mV VCC 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V MIN 0.245 0.495 0.619 TYP 1/4 1/2 5/8 MAX 0.255 0.505 0.631 UNIT N/A (see Note 1) N/A (see Note 1) N/A (see Note 1) N/A (see Note 1) 0.061 0.122 0.184 0.245 0.367 0.495 1/16 1/8 3/16 1/4 3/8 1/2 40 4 3 60 6 5 160 20 15 ?s 0.065 0.128 0.192 0.255 0.383 0.505 VCC N/A (see Note 1) NOTES: 1. The level is not available due to the analog input voltage range of the operational amplifier. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 53 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) operational amplifier OA feedback network, non-inverting amplifier mode (OAFCx = 4. MSP430x22x4 only) PARAMETER TEST CONDITIONS OAFBRx = 0 OAFBRx = 1 OAFBRx = 2 OAFBRx = 3 G Gain OAFBRx = 4 OAFBRx = 5 OAFBRx = 6 OAFBRx = 7 THD Total Harmonic Distortion/ Nonlinearity all gains VCC 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V 3V MIN 0.998 1.328 1.985 2.638 3.94 5.22 7.76 15.0 TYP 1.00 1.334 2.001 2.667 4.00 5.33 7.97 15.8 -60 -70 dB MAX 1.002 1.340 2.017 2.696 4.06 5.44 8.18 16.6 UNIT tSettle Settling time (see Note 1) all power modes 2.2 V/3 V 7 12 ?s NOTES: 1. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster. operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6, see Note 1, MSP430x22x4 only) PARAMETER TEST CONDITIONS OAFBRx = 1 OAFBRx = 2 OAFBRx = 3 G Gain OAFBRx = 4 OAFBRx = 5 OAFBRx = 6 OAFBRx = 7 THD Total Harmonic Distortion/ Nonlinearity all gains VCC 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V 3V MIN -0.345 -1.023 -1.712 -3.10 -4.51 -7.37 -16.3 TYP -0.335 -1.002 -1.668 -3.00 -4.33 -6.97 -14.8 -60 -70 dB MAX -0.325 -0.979 -1.624 -2.90 -4.15 -6.57 -13.1 UNIT tSettle Settling time (see Note 2) all power modes 2.2 V/3 V 7 12 ?s NOTES: 1. This includes the 2 OA configuration "inverting amplifier with input buffer". Both OA needs to be set to the same power mode OAPMx. 2. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster. 54 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Flash Memory PARAMETER VCC(PGM/ ERASE) fFTG IPGM IERASE tCPT tCMErase tRetention tWord tBlock, 0 tBlock, 1-63 tBlock, End tMass Erase tSeg Erase Program and Erase supply voltage Flash Timing Generator frequency Supply current from VCC during program Supply current from VCC during erase Cumulative program time (see Note 1) Cumulative mass erase time Program/Erase endurance Data retention duration Word or byte program time Block program time for 1st byte or word Block program time for each additional byte or word Block program end-sequence wait time Mass erase time Segment erase time see Note 2 TJ = 25?C 2.2 V/3.6 V 2.2 V/3.6 V 2.2 V/3.6 V 2.2 V/3.6 V 20 104 100 30 25 18 6 10593 4819 tFTG 105 TEST CONDITIONS VCC MIN 2.2 257 1 1 TYP MAX 3.6 476 5 7 10 UNIT V kHz mA mA ms ms cycles years NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG). RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(RAMh) RAM retention supply voltage (see Note 1) CPU halted 1.6 V NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 55 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) JTAG and Spy-Bi-Wire Interface PARAMETER fSBW tSBW,Low tSBW,En tSBW,Ret fTCK Spy-Bi-Wire input frequency Spy-Bi-Wire low clock pulse length Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge, see Note 1) Spy-Bi-Wire return to normal operation time TCK input frequency (see Note 2) TEST CONDITIONS VCC 2.2 V / 3 V 2.2 V / 3 V 2.2 V/ 3 V 2.2 V/ 3 V 2.2 V 3V 15 0 0 MIN 0 0.025 TYP MAX 20 15 1 100 5 10 UNIT MHz us us us MHz MHz RInternal Internal pull-down resistance on TEST 2.2 V/ 3 V 25 60 90 k NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge. 2. fTCK may be restricted to meet the timing requirements of the module selected. JTAG Fuse (see Note 1) PARAMETER VCC(FB) VFB IFB tFB Supply voltage during fuse-blow condition Voltage level on TEST for fuse-blow Supply current into TEST during fuse blow Time to blow fuse TEST CONDITIONS TA = 25?C VCC MIN 2.5 6 7 100 1 TYP MAX UNIT V V mA ms NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test and emulation feature is possible and is switched to bypass mode. 56 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 APPLICATION INFORMATION Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt-trigger P1REN.x Pad Logic DVSS DVCC P1DIR.x 0 1 Direction 0: Input 1: Output 0 1 1 P1OUT.x Module X OUT P1SEL.x P1IN.x 0 1 P1.0/TACLK/ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2 EN Module X IN D P1IE.x P1IRQ.x P1IFG.x P1SEL.x P1IES.x Q EN Set Interrupt Edge Select Port P1 (P1.0 to P1.3) pin functions PIN NAME (P1.X) P1.0/ TACLK/ADC10CLk CONTROL BITS / SIGNALS X 0 P1.0 (I/O) Timer_A3.TACLK ADC10CLK P1.1/TA0 1 P1.1 (I/O) Timer_A3.CCI0A Timer_A3.TA0 P1.2/TA1 2 P1.2 (I/O) Timer_A3.CCI0A Timer_A3.TA0 P1.3/TA2 3 P1.3 (I/O) Timer_A3.CCI0A Timer_A3.TA0 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. FUNCTION P1DIR.x I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 P1SEL.x 0 1 1 0 1 1 0 1 1 0 1 1 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 57 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P1 pin schematic: P1.4 to P1.6, input/output with Schmitt-trigger and in-system access features Pad Logic P1REN.x DVSS DVCC P1DIR.x 0 1 Direction 0: Input 1: Output 0 1 1 P1OUT.x Module X OUT P1SEL.x P1IN.x 0 1 Bus Keeper EN EN P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI Module X IN D P1IE.x P1IRQ.x P1IFG.x P1SEL.x P1IES.x To JTAG From JTAG Q EN Set Interrupt Edge Select Port P1 (P1.4 to P1.6) pin functions PIN NAME (P1.X) P1.4/SMCLK/TCK CONTROL BITS / SIGNALS X 4 P1.4 (I/O) SMCLK TCK P1.5/TA0/TMS 5 P1.5 (I/O) Timer_A3.TA0 TMS P1.6/TA1/TDI/TCLK 6 P1.6 (I/O) Timer_A3.TA1 TDI/TCLK (see Note 3) Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. Function controlled by JTAG. FUNCTION P1DIR.x I: 0; O: 1 1 X I: 0; O: 1 1 X I: 0; O: 1 1 X P1SEL.x 0 1 X 0 1 X 0 1 X 4-Wire JTAG 0 0 1 0 0 1 0 0 1 58 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P1 pin schematic: P1.7, input/output with Schmitt-trigger and in-system access features Pad Logic P1REN.7 DVSS DVCC P1DIR.7 0 1 Direction 0: Input 1: Output 0 1 1 P1OUT.7 Module X OUT P1SEL.7 P1IN.7 0 1 Bus Keeper EN EN P1.7/TA2/TDO/TDI Module X IN D P1IE.7 P1IRQ.7 P1IFG.7 P1SEL.7 P1IES.7 To JTAG From JTAG From JTAG From JTAG (TDO) Q EN Set Interrupt Edge Select Port P1 (P1.7) pin functions PIN NAME (P1.X) P1.7/TA2/TDO/TDI CONTROL BITS / SIGNALS X 7 P1.7 (I/O) Timer_A3.TA2 TDO/TDI (see Note 3) Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. Function controlled by JTAG. FUNCTION P1DIR.x I: 0; O: 1 1 X P1SEL.x 0 1 X 4-Wire JTAG 0 0 1 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 59 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P2 pin schematic: P2.0, P2.2, input/output with Schmitt-trigger Pad Logic To ADC 10 INCHx = y ADC10AE0.y P2REN.x DVSS DVCC P2DIR.x 0 1 Direction 0: Input 1: Output 0 1 1 P2OUT.x Module X OUT P2SEL.x P2IN.x 0 1 Bus Keeper EN EN P2.0/ACLK/A0/OA0I0 P2.2/TA0/A2/OA0I1 Module X IN D P2IE.x P2IRQ.x P2IFG.x P2SEL.x P2IES.x Q EN Set Interrupt Edge Select + OA0 - Port P2 (P2.0, P2.2) pin functions PIN NAME (P2.X) P2.0/ACLK/A0/OA0I0 CONTROL BITS / SIGNALS X 0 Y 0 P2.0 (I/O) ACLK A0/OA0I0 (see Note 3) P2.2/TA0/A2/OA0I1 2 2 P2.2 (I/O) Timer_A3.CCI0B Timer_A3.TA0 A2/OA0I1 (see Note 3) FUNCTION P2DIR.x I: 0; O: 1 1 X I: 0; O: 1 0 1 X P2SEL.x 0 1 X 0 1 1 X ADC10AE0.y 0 0 1 0 0 0 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 60 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P2 pin schematic: P2.1, input/output with Schmitt-trigger Pad Logic To ADC 10 INCHx = 1 ADC10AE0.1 P2REN.1 DVSS DVCC P2DIR.1 0 1 Direction 0: Input 1: Output 0 1 1 P2OUT.1 Module X OUT P2SEL.1 P2IN.1 0 1 Bus Keeper EN EN P2.1/TAINCLK/SMCLK/ A1/OA0O Module X IN D P2IE.1 P2IRQ.1 P2IFG.1 P2SEL.1 P2IES.1 OAADCx OAFCx OAPMx Q EN Set Interrupt Edge Select + OA0 - 1 (OAADCx = 10 or OAFCx = 000) and OAPMx > 00 To OA0 Feedback Network 1 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 61 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P2 pin schematic: P2.3, input/output with Schmitt-trigger SREF2 0 1 VSS Pad Logic To ADC 10 VR- To ADC 10 INCHx = 3 ADC10AE0.3 P2REN.3 DVSS DVCC P2DIR.3 0 1 Direction 0: Input 1: Output 0 1 1 P2OUT.3 Module X OUT P2SEL.3 P2IN.3 0 1 Bus Keeper EN EN P2.3/TA1/ A3/VREF- /VeREF- / OA1I1/OA1O Module X IN D P2IE.3 P2IRQ.3 P2IFG.3 P2SEL.3 P2IES.3 Q EN Set Interrupt Edge Select + OA1 - 1 OAADCx OAFCx OAPMx (OAADCx = 10 or OAFCx = 000) and OAPMx > 00 To OA1 Feedback Network 1 62 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P2 (P2.1) pin functions PIN NAME (P2.X) P2.1/TAINCLK/SMCLK /A1/OA0O CONTROL BITS / SIGNALS X 1 Y 1 P2.1 (I/O) Timer_A3.INCLK SMCLK A1/OA0O (see Note 3) FUNCTION P2DIR.x I: 0; O: 1 0 1 X P2SEL.x 0 1 1 X ADC10AE0.y 0 0 0 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. Port P2 (P2.3) pin functions PIN NAME (P2.X) P2.3/TA1/ A3/VREF-/VeREF-/ OA1I1/OA1O CONTROL BITS / SIGNALS X 3 Y 3 P2.3 (I/O) Timer_A3.CCI1B Timer_A3.TA1 A3/VREF-/VeREF-/OA1I1/OA1O (see Note 3) FUNCTION P2DIR.x I: 0; O: 1 0 1 X P2SEL.x 0 1 1 X ADC10AE0.y 0 0 0 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 63 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P2 pin schematic: P2.4, input/output with Schmitt-trigger Pad Logic To/from ADC10 positive reference To ADC10 INCHx = 4 ADC10AE0.4 P2REN.4 DVSS DVCC P2DIR.4 0 1 Direction 0: Input 1: Output 0 1 1 P2OUT.4 Module X OUT P2SEL.4 P2IN.4 0 1 Bus Keeper EN EN P2.4/TA2/ A4/VREF+/VeREF+/ OA1I0 Module X IN D P2IE.4 P2IRQ.4 P2IFG.4 P2SEL.4 P2IES.4 Q EN Set Interrupt Edge Select + OA1 - Port P2 (P2.4) pin functions PIN NAME (P2.X) P2.4/TA2/ A4/VREF+/VeREF+/ OA1I0 CONTROL BITS / SIGNALS X 4 Y 4 P2.4 (I/O) Timer_A3.TA2 FUNCTION P2DIR.x I: 0; O: 1 1 P2SEL.x 0 1 ADC10AE0.y 0 0 A4/VREF+/VeREF+/OA1I0 (see Note 3) X X 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 64 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P2 pin schematic: P2.5, input/output with Schmitt-trigger and external ROSC for DCO Pad Logic To DCO DCOR P1REN.x DVSS DVCC P1DIR.x 0 1 Direction 0: Input 1: Output 0 1 1 P1OUT.x Module X OUT P1SEL.x P1IN.x 0 1 Bus Keeper EN EN P2.5/ROSC Module X IN D P1IE.x P1IRQ.x P1IFG.x P1SEL.x P1IES.x Q EN Set Interrupt Edge Select Port P2 (P2.5) pin functions PIN NAME (P2.X) P2.5/ROSC CONTROL BITS / SIGNALS X 5 P2.5 (I/O) N/A DVSS ROSC FUNCTION P2DIR.x I: 0; O: 1 0 1 P2SEL.x 0 1 1 DCOR 0 0 0 X X 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 65 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P2 pin schematic: P2.6, input/output with Schmitt-trigger and crystal oscillator input BCSCTL3.LFXT1Sx = 11 LFXT1 Oscillator P2.7/XOUT LFXT1 off LFXT1CLK P2SEL.7 P2REN.6 0 1 Pad Logic DVSS DVCC P2DIR.6 0 1 Direction 0: Input 1: Output 0 1 1 P2OUT.6 Module X OUT P2SEL.6 P2IN.6 0 1 Bus Keeper EN EN P2.6/XIN Module X IN D P2IE.6 P2IRQ.6 P2IFG.6 P2SEL.6 P2IES.6 Q EN Set Interrupt Edge Select Port P2 (P2.6) pin functions PIN NAME (P2.X) P2.6/XIN CONTROL BITS / SIGNALS X 6 P2.6 (I/O) XIN Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. FUNCTION P2DIR.x I: 0; O: 1 X P2SEL.x 0 1 66 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P2 pin schematic: P2.7, input/output with Schmitt-trigger and crystal oscillator output BCSCTL3.LFXT1Sx = 11 LFXT1 Oscillator LFXT1 off LFXT1CLK P2SEL.6 P2REN.7 0 1 From P2.6/XIN Pad Logic P2.6/XIN DVSS DVCC P2DIR.7 0 1 Direction 0: Input 1: Output 0 1 1 P2OUT.7 Module X OUT P2SEL.7 P2IN.7 0 1 Bus Keeper EN EN P2.7/XOUT Module X IN D P2IE.7 P2IRQ.7 P2IFG.7 P2SEL.7 P2IES.7 Q EN Set Interrupt Edge Select Port P2 (P2.7) pin functions PIN NAME (P2.X) XOUT/P2.7 CONTROL BITS / SIGNALS X 6 P2.7 (I/O) XOUT (see Note 3) FUNCTION P2DIR.x I: 0; O: 1 X P2SEL.x 0 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this pin after reset. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 67 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P3 pin schematic: P3.0, input/output with Schmitt-trigger Pad Logic To ADC 10 INCHx = 5 ADC10AE0.5 P3REN.0 DVSS DVCC P3DIR.0 USCI Direction Control P3OUT.0 Module X OUT P3SEL.0 P3IN.0 EN Module X IN D 0 1 Direction 0: Input 1: Output 0 1 1 0 1 Bus Keeper EN P3.0/UC1STE/UC0CLK/A5 Port P3 (P3.0) pin functions PIN NAME (P3.X) P3.0/ UC1STE/UC0CLK/A5 CONTROL BITS / SIGNALS X 0 Y 5 P3.0 (I/O) UC1STE/UC0CLK (see Notes 3, 4) FUNCTION P3DIR.x I: 0; O: 1 X P3SEL.x 0 1 ADC10AE0.y 0 0 A5 (see Note 5) X X 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. The pin direction is controlled by the USCI module. 4. UC0CLK function takes precedence over UC1STE function. If the pin is required as UC0CLK input or output USCI1 will be forced to 3-wire SPI mode if 4-wire SPI mode is selected. 5. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 68 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P3 pin schematic: P3.1 to P3.5, input/output with Schmitt-trigger DVSS P3REN.x Pad Logic DVSS DVCC P3DIR.x USCI Direction Control P3OUT.x Module X OUT P3SEL.x P3IN.x EN Module X IN D 0 1 Direction 0: Input 1: Output 0 1 1 0 1 Bus Keeper EN P3.1/UC1SIMO/UC1SCL P3.2/UC1SOMI/UC1SDA P3.3/UC1CLK/UC0STE P3.4/UC0TXD/UC0SIMO P3.5/UC0RXD/UC0SOMI Port P3 (P3.1 to P3.5) pin functions PIN NAME (P3.X) P3.1/ UC1SIMO/UC1SDA P3.2/ UC1SOMI/UC1SCL P3.3/ UC1CLK/UC0STE P3.4/ UC0TXD/UC0SIMO P3.5/ UC0RXD/UC0SOMI CONTROL BITS / SIGNALS X 1 1 1 1 1 P3.1 (I/O) UC1SIMO/UC1SDA (see Note 3) P3.2 (I/O) UC1SOMI/UC1SCL (see Note 3) P3.3 (I/O) UC1CLK/UC0STE (see Notes 3, 4) P3.4 (I/O) UC0TXD/UC0SIMO (see Note 3) P3.5 (I/O) UC0RXD/UC0SOMI (see Note 3) FUNCTION P3DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P3SEL.x 0 1 0 1 0 1 0 1 0 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. The pin direction is controlled by the USCI module. 4. UC1CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output USCI0 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 69 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P3 pin schematic: P3.6 to P3.7, input/output with Schmitt-trigger Pad Logic To ADC 10 INCHx = y ADC10AE0.y P3REN.x DVSS DVCC P3DIR.x 0 1 Direction 0: Input 1: Output 0 1 1 P3OUT.x Module X OUT P3SEL.x P3IN.x 0 1 Bus Keeper EN EN P3.6/A6/OA0I2 P3.7/A7/OA1I2 Module X IN D + OA0/1 - Port P3 (P3.6, P3.7) pin functions PIN NAME (P3.X) P3.6/A6/OA0I2 P3.7/A7/OA1I2 CONTROL BITS / SIGNALS X 6 7 Y 6 7 P3.6 (I/O) A6/OA0I2 (see Note 5) P3.7 (I/O) A7/OA1I2 (see Note 5) FUNCTION P3DIR.x I: 0; O: 1 X I: 0; O: 1 X P3SEL.x 0 X 0 X ADC10AE0.y 0 1 0 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. The pin direction is controlled by the USCI module. 4. UC1CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output USCI0 will be forced to 3-wire SPI mode if 4-wire SPI mode is selected. 5. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 70 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P4 pin schematic: P4.0 to P4.2, input/output with Schmitt-trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 Pad Logic P4REN.x DVSS DVCC P4DIR.x 0 1 Direction 0: Input 1: Output 0 1 1 P4OUT.x Module X OUT P4SEL.x P4IN.x 0 1 Bus Keeper EN EN P4.0/TB0 P4.1/TB1 P4.2/TB2 Module X IN D Port P4 (P4.0 to P4.2) pin functions PIN NAME (P4.X) P4.0/TB0 CONTROL BITS / SIGNALS X 0 P4.0 (I/O) Timer_B3.CCI0A Timer_B3.TB0 P4.1/TB1 1 P4.1 (I/O) Timer_B3.CCI1A Timer_B3.TB1 P4.2/TB2 2 P4.2 (I/O) Timer_B3.CCI2A Timer_B3.TB2 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. FUNCTION P4DIR.x I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 P4SEL.x 0 1 1 0 1 1 0 1 1 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 71 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P4 pin schematic: P4.3 to P4.4, input/output with Schmitt-trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 To ADC 10 INCHx = 8+y Pad Logic ADC10AE1.y P4REN.x DVSS DVCC P4DIR.x 0 1 Direction 0: Input 1: Output 0 1 1 P4OUT.x Module X OUT P4SEL.x P4IN.x 0 1 Bus Keeper EN EN P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O Module X IN D + OA0/1 - 1 OAADCx OAPMx OAADCx = 01 and OAPMx > 00 To OA0/1 Feedback Network 1 If OAADCx = 11 and not OAFCx = 000 the ADC input A12 or A13 is internally connected to the OA0 or OA1 output respectively and the connections from the ADC and the operational amplifiers to the pad are disabled. 72 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P4 (P4.3 to P4.4) pin functions PIN NAME (P4.X) P4.3/TB0/A12/OA0O CONTROL BITS / SIGNALS X 3 Y 4 P4.3 (I/O) Timer_B3.CCI0B Timer_B3.TB0 A12/OA0O (see Note 3) P4.4/TB1/A13/OA1O 4 5 P4.4 (I/O) Timer_B3.CCI1B Timer_B3.TB1 FUNCTION P4DIR.x I: 0; O: 1 0 1 X I: 0; O: 1 0 1 P4SEL.x 0 1 1 X 0 1 1 ADC10AE1.y 0 0 0 1 0 0 0 A13/OA1O (see Note 3) X X 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 73 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P4 pin schematic: P4.5, input/output with Schmitt-trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 To ADC 10 INCHx = 14 ADC10AE1.6 Pad Logic P4REN.5 DVSS DVCC P4DIR.5 0 1 Direction 0: Input 1: Output 0 1 1 P4OUT.5 Module X OUT P4SEL.5 P4IN.5 0 1 Bus Keeper EN EN P4.5/TB3/A14/OA0I3 Module X IN D + OA0 - 74 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P4 (P4.5) pin functions PIN NAME (P4.X) P4.5/TB3/A14/OA0I3 CONTROL BITS / SIGNALS X 5 Y 6 P4.5 (I/O) Timer_B3.TB2 A14/OA0I3 (see Note 3) FUNCTION P4DIR.x I: 0; O: 1 1 X P4SEL.x 0 1 X ADC10AE1.y 0 0 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 75 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P4 pin schematic: P4.6, input/output with Schmitt-trigger Pad Logic To ADC 10 INCHx = 15 ADC10AE1.7 P4REN.6 DVSS DVCC P4DIR.6 0 1 Direction 0: Input 1: Output 0 1 1 P4OUT.6 Module X OUT P4SEL.6 P4IN.6 0 1 Bus Keeper EN EN P4.6/TBOUTH/ A15/OA1I3 Module X IN D + OA1 - Port P4 (P4.6) pin functions PIN NAME (P4.X) P4.6/TBOUTH/ A15/OA1I3 CONTROL BITS / SIGNALS X 6 Y 7 P4.6 (I/O) TBOUTH DVSS A15/OA1I3 (see Note 3) FUNCTION P4DIR.x I: 0; O: 1 0 1 X P4SEL.x 0 1 1 X ADC10AE1.y 0 0 0 1 Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. 3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 76 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Port P4 pin schematic: P4.7, input/output with Schmitt-trigger DVSS P4REN.x Pad Logic DVSS DVCC P4DIR.x 0 1 Direction 0: Input 1: Output 0 1 1 P4OUT.x Module X OUT P4SEL.x P4IN.x 0 1 Bus Keeper EN EN P4.7/TBCLK Module X IN D Port P4 (P4.7) pin functions PIN NAME (P4.X) P4.7/TBCLK CONTROL BITS / SIGNALS X 7 P4.7 (I/O) Timer_B3.TBCLK DVSS Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don't care. FUNCTION P4DIR.x I: 0; O: 1 0 1 P4SEL.x 0 1 1 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 77 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 JTAG fuse check mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITEST ITF Figure 28. Fuse Check Mode Current, MSP430F22xx NOTE: The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the bootstrap loader section for more information. 78 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504A - JULY 2006 - REVISED DECEMBER 2006 Data Sheet Revision History Literature Number SLAS504 SLAS504A Preliminary data sheet release. Production data sheet release. Updated specification and added characterization graphs. Updated/corrected port pin schematics. Summary NOTE: The referring page and figure numbers are referred to the respective document revision. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 79 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 PACKAGING INFORMATION Orderable Device MSP430F2232IDA MSP430F2232IDAR MSP430F2232IRHAR MSP430F2232IRHAT MSP430F2232TDA MSP430F2232TDAR MSP430F2232TRHAR MSP430F2232TRHAT MSP430F2234IDA MSP430F2234IDAR MSP430F2234IRHAR MSP430F2234IRHAT MSP430F2234TDA MSP430F2234TDAR MSP430F2234TRHAR MSP430F2234TRHAT MSP430F2252IDA MSP430F2252IDAR MSP430F2252IRHAR MSP430F2252IRHAT MSP430F2252TDA MSP430F2252TDAR MSP430F2252TRHAR MSP430F2252TRHAT MSP430F2254IDA MSP430F2254IDAR Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PREVIEW PREVIEW ACTIVE ACTIVE Package Type TSSOP TSSOP QFN QFN TSSOP TSSOP QFN QFN TSSOP TSSOP QFN QFN TSSOP TSSOP QFN QFN TSSOP TSSOP QFN QFN TSSOP TSSOP QFN QFN TSSOP TSSOP Package Drawing DA DA RHA RHA DA DA RHA RHA DA DA RHA RHA DA DA RHA RHA DA DA RHA RHA DA DA RHA RHA DA DA Pins Package Eco Plan (2) Qty 38 38 40 40 38 38 40 40 38 38 40 40 38 38 40 40 38 38 40 40 38 38 40 40 38 38 40 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-3-260C-168 HR Level-3-260C-168 HR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-3-260C-168 HR Level-3-260C-168 HR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-3-260C-168 HR Level-3-260C-168 HR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Call TI Level-3-260C-168 HR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-3-260C-168 HR Level-3-260C-168 HR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Call TI Call TI Level-2-260C-1 YEAR Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 250 40 TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 250 40 TBD TBD Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 Orderable Device MSP430F2254IRHAR MSP430F2254IRHAT MSP430F2254TDA MSP430F2254TDAR MSP430F2254TRHAR MSP430F2254TRHAT MSP430F2272IDA MSP430F2272IDAR MSP430F2272IRHAR MSP430F2272IRHAT MSP430F2272TDA MSP430F2272TDAR MSP430F2272TRHAR MSP430F2272TRHAT MSP430F2274IDA MSP430F2274IDAR MSP430F2274IRHAR MSP430F2274IRHAT MSP430F2274TDA MSP430F2274TDAR MSP430F2274TRHAR MSP430F2274TRHAT (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type QFN QFN TSSOP TSSOP QFN QFN TSSOP TSSOP QFN QFN TSSOP TSSOP QFN QFN TSSOP TSSOP QFN QFN TSSOP TSSOP QFN QFN Package Drawing RHA RHA DA DA RHA RHA DA DA RHA RHA DA DA RHA RHA DA DA RHA RHA DA DA RHA RHA Pins Package Eco Plan (2) Qty 40 40 38 38 40 40 38 38 40 40 38 38 40 40 38 38 40 40 38 38 40 40 2500 Green (RoHS & no Sb/Br) 250 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-3-260C-168 HR Level-3-260C-168 HR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-3-260C-168 HR Level-3-260C-168 HR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-3-260C-168 HR Level-3-260C-168 HR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-3-260C-168 HR Level-3-260C-168 HR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-3-260C-168 HR Level-3-260C-168 HR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-3-260C-168 HR Level-3-260C-168 HR 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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